18523637. NON-PLANAR INTEGRATED CIRCUIT STRUCTURES HAVING MITIGATED SOURCE OR DRAIN ETCH FROM REPLACEMENT GATE PROCESS simplified abstract (Intel Corporation)

NON-PLANAR INTEGRATED CIRCUIT STRUCTURES HAVING MITIGATED SOURCE OR DRAIN ETCH FROM REPLACEMENT GATE PROCESS

Organization Name

Intel Corporation

Inventor(s)

Jun Sung Kang of Portland OR (US)

Kai Loon Cheong of Beaverton OR (US)

Erica J. Thompson of Beaverton OR (US)

Biswajeet Guha of Hillsboro OR (US)

William Hsu of Hillsboro OR (US)

Dax M. Crum of Beaverton OR (US)

Tahir Ghani of Portland OR (US)

Bruce Beattie of Portland OR (US)

NON-PLANAR INTEGRATED CIRCUIT STRUCTURES HAVING MITIGATED SOURCE OR DRAIN ETCH FROM REPLACEMENT GATE PROCESS - A simplified explanation of the abstract

This abstract first appeared for US patent application 18523637 titled 'NON-PLANAR INTEGRATED CIRCUIT STRUCTURES HAVING MITIGATED SOURCE OR DRAIN ETCH FROM REPLACEMENT GATE PROCESS

Simplified Explanation

The patent application describes non-planar integrated circuit structures with mitigated source or drain etch from replacement gate process.

• Integrated circuit structure includes a fin or nanowire
• Gate stack with gate dielectric and gate electrode
• Dielectric spacers along sides of gate stack
• Insulating material between fin/nanowire and dielectric spacers
• Epitaxial source or drain structures on either side of gate stack

Potential Applications

This technology could be applied in the semiconductor industry for advanced integrated circuits, such as in high-performance computing, mobile devices, and IoT applications.

Problems Solved

This technology helps mitigate source or drain etch issues during the replacement gate process, improving the reliability and performance of integrated circuits.

Benefits

- Enhanced reliability of integrated circuits - Improved performance of semiconductor devices - Potential for higher integration density

Potential Commercial Applications

• "Advanced Integrated Circuit Structures for Enhanced Performance and Reliability"

Possible Prior Art

There may be prior art related to non-planar integrated circuit structures and mitigation of source or drain etch issues, but specific examples are not provided in the abstract.

Unanswered Questions

How does this technology compare to existing methods for mitigating source or drain etch issues in integrated circuits?

This article does not provide a direct comparison with existing methods, leaving the reader to wonder about the specific advantages of this approach over others.

What are the specific performance improvements that can be expected from implementing this technology in integrated circuits?

The article does not delve into the specific performance enhancements that can be achieved by using this technology, leaving room for further exploration into the potential benefits for semiconductor devices.

Original Abstract Submitted

Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process are described. For example, an integrated circuit structure includes a fin or nanowire. A gate stack is over the fin or nanowire. The gate stack includes a gate dielectric and a gate electrode. A first dielectric spacer is along a first side of the gate stack, and a second dielectric spacer is along a second side of the gate stack. The first and second dielectric spacers are over at least a portion of the fin or nanowire. An insulating material is vertically between and in contact with the portion of the fin or nanowire and the first and second dielectric spacers. A first epitaxial source or drain structure is at the first side of the gate stack, and a second epitaxial source or drain structure is at the second side of the gate stack.