18518167. SYSTEMS AND METHODS FOR INTEGRATED CIRCUIT LAYOUT simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)
SYSTEMS AND METHODS FOR INTEGRATED CIRCUIT LAYOUT
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Qingwen Deng of San Jose CA (US)
SYSTEMS AND METHODS FOR INTEGRATED CIRCUIT LAYOUT - A simplified explanation of the abstract
This abstract first appeared for US patent application 18518167 titled 'SYSTEMS AND METHODS FOR INTEGRATED CIRCUIT LAYOUT
Simplified Explanation
The method described in the patent application involves receiving a behavioral description of an IC design, synthesizing it, generating a layout based on the description, performing timing analysis, and updating the layout by inserting transistor-based or non-transistor-based cells.
- The method involves receiving and synthesizing a behavioral description of an IC design.
- Based on the synthesized description, a layout for the IC design is generated.
- Timing analysis is performed on the layout.
- A first cell library with transistor-based cells and associated delay values is accessed.
- A second cell library with non-transistor-based cells and associated delay values is accessed.
- The layout is updated by inserting either transistor-based or non-transistor-based cells.
Potential Applications
- Integrated Circuit (IC) design
- Semiconductor industry
- Electronic device manufacturing
Problems Solved
- Efficient layout design for ICs
- Optimizing timing analysis
- Utilizing different types of cells in IC design
Benefits
- Improved performance of IC designs
- Enhanced efficiency in layout generation
- Flexibility in choosing cell types for design optimization
Original Abstract Submitted
A method for providing an IC design is disclosed. The method includes receiving and synthesizing a behavioral description of an IC design; generating, based on the synthesized behavioral description, a layout for the IC design; performing at least a timing analysis on the layout; accessing, based on the timing analysis, a first cell library including a plurality of transistor-based cells, each having one or more transistors and associated with a respective first delay value; accessing, based on the timing analysis, a second cell library including a plurality of non-transistor-based cells, each having no transistor and associated with a respective second delay value; and updating the layout by at least one of inserting one or more of the plurality of transistor-based cells or inserting one or more of the plurality of non-transistor-based cells.
