18516373. HYBRID CONDUCTIVE STRUCTURES simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

HYBRID CONDUCTIVE STRUCTURES

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Shuen-Shin Liang of Hsinchu County (TW)

Chij-chien Chi of Hsinchu City (TW)

Yi-Ying Liu of Hsinchu City (TW)

Chia-Hung Chu of Hsinchu City (TW)

Hsu-Kai Chang of Hsinchu (TW)

Cheng-Wei Chang of Taipei (TW)

Chein-Shun Liao of New Taipei City (TW)

Keng-chu Lin of Ping-Tung (TW)

KAi-Ting Huang of Hsinchu (TW)

HYBRID CONDUCTIVE STRUCTURES - A simplified explanation of the abstract

This abstract first appeared for US patent application 18516373 titled 'HYBRID CONDUCTIVE STRUCTURES

Simplified Explanation

The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.

• Deposit first dielectric on substrate with gate and S/D structures
• Form opening in dielectric to expose S/D structures
• Deposit ruthenium metal on bottom and sidewall surfaces of opening
• Deposit cobalt metal to fill the opening
• Reflow cobalt metal and planarize to form coplanar S/D structures

Potential Applications

The technology described in this patent application could be applied in the semiconductor industry for the manufacturing of advanced integrated circuits.

Problems Solved

1. Improved conductivity and reliability of S/D structures in semiconductor devices. 2. Enhanced performance and durability of metallization layers in integrated circuits.

Benefits

1. Increased efficiency and speed of semiconductor devices. 2. Enhanced overall performance and longevity of integrated circuits.

Potential Commercial Applications

Optimizing metallization layers in semiconductor devices for improved performance and reliability.

Possible Prior Art

One possible prior art could be the use of different metal combinations for forming metallization layers in semiconductor devices, but the specific combination of ruthenium metal liner and cobalt metal fill as described in this patent application may be novel.

How does this technology compare to existing methods for forming metallization layers in semiconductor devices?

This article does not provide a direct comparison to existing methods for forming metallization layers in semiconductor devices. It would be interesting to know the specific advantages and disadvantages of this new method compared to traditional techniques.

What are the potential challenges or limitations of implementing this technology in large-scale semiconductor manufacturing processes?

The article does not address the potential challenges or limitations of implementing this technology in large-scale semiconductor manufacturing processes. It would be important to understand any obstacles that may arise when scaling up this method for mass production.

Original Abstract Submitted

The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.