18514716. SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
Organization Name
Inventor(s)
Young-Jin Kwon of Suwon-si (KR)
Geun Won Lim of Yongin-si (KR)
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18514716 titled 'SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
Simplified Explanation
The patent application describes a semiconductor device with a unique structure involving a cell array region, an extension region, contact regions, through regions, a mold structure, gate electrodes, a channel structure, gate contacts, and insulating patterns.
- Mold structure with alternating first insulating patterns and gate electrodes on a substrate.
- Channel structure intersecting gate electrodes in the cell array region.
- Gate contacts on the mold structure in contact regions connected to gate electrodes.
- Second insulating patterns with different material stacked alternately with first insulating patterns in through regions.
Potential Applications
- Advanced semiconductor devices
- Integrated circuits
- Memory storage devices
Problems Solved
- Enhanced performance and efficiency of semiconductor devices
- Improved integration of components
- Reduction of signal interference
Benefits
- Higher processing speeds
- Increased storage capacity
- Improved overall device performance
Original Abstract Submitted
A semiconductor device, in which a cell array region and an extension region are arranged along a first direction, and in which contact regions and through regions are alternately arranged along the first direction in the extension region, including: a mold structure including a plurality of first insulating patterns and a plurality of gate electrodes, which are alternately stacked on a first substrate; a channel structure penetrating the mold structure in the cell array region to intersect the plurality of gate electrodes; respective gate contacts that are on the mold structure in the contact regions and are connected to each of the gate electrodes; and a plurality of second insulating patterns, the second insulating patterns being stacked alternately with the first insulating patterns in the mold structure in the through regions, the plurality of second insulating patterns including a different material from the plurality of first insulating patterns.
