18514356. BASE LAYOUT CELL simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)

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BASE LAYOUT CELL

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Shang-Hsuan Chiu of Hsinchu (TW)

Chih-Liang Chen of Hsinchu (TW)

Hui-Zhong Zhuang of Kaohsiung City (TW)

Chi-Yu Lu of New Taipei City (TW)

Kuang-Ching Chang of Hsinchu (TW)

BASE LAYOUT CELL - A simplified explanation of the abstract

This abstract first appeared for US patent application 18514356 titled 'BASE LAYOUT CELL

Simplified Explanation

The patent application describes systems, methods, and devices related to an engineering change order (ECO) base layout cell used in electronic design.

  • The base layout cell includes metal layer regions, conductive gate patterns, oxide definition (OD) patterns, metal-zero layer over oxide-definition (metal-zero) patterns, at least one cut metal layer (CMD) pattern, and at least one via region.
  • The base layout cell can be implemented in at least two non-identical functional cells, each with different interconnection conductive patterns connecting metal-zero structures.
  • The first functional cell connects metal-zero structures corresponding to at least two metal-zero patterns in a first layout, while the second functional cell connects metal-zero structures corresponding to at least two metal-zero patterns in a second layout.

Potential Applications

  • Electronic design automation
  • Integrated circuit design
  • Semiconductor manufacturing

Problems Solved

  • Efficient implementation of engineering change orders
  • Flexibility in designing electronic circuits
  • Optimization of interconnection patterns

Benefits

  • Streamlined design processes
  • Increased design flexibility
  • Enhanced productivity in electronic design


Original Abstract Submitted

Systems, methods and devices are provided, which can include an engineering change order (ECO) base. A base layout cell includes metal layer regions, conductive gate patterns arranged above metal layer regions; oxide definition (OD) patterns, metal-zero layer over oxide-definition (metal-zero) patterns, at least one cut metal layer (CMD) pattern; and at least one via region. The base layout cell can be implemented in at least two non-identical functional cells. A first functional cell of the at least two non-identical functional cells includes first interconnection conductive patterns arranged connecting metal-zero structures corresponding to at least two metal-zero patterns in a first layout, and a second functional cell of the at least two non-identical functional cells includes second interconnection conductive patterns arranged connecting metal-zero structures corresponding to at least two metal-zero patterns in a second layout.

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