18513942. ROUGH BUFFER LAYER FOR GROUP III-V DEVICES ON SILICON simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)
ROUGH BUFFER LAYER FOR GROUP III-V DEVICES ON SILICON
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Kuei-Ming Chen of New Taipei City (TW)
Chi-Ming Chen of Zhubei City (TW)
ROUGH BUFFER LAYER FOR GROUP III-V DEVICES ON SILICON - A simplified explanation of the abstract
This abstract first appeared for US patent application 18513942 titled 'ROUGH BUFFER LAYER FOR GROUP III-V DEVICES ON SILICON
Simplified Explanation
The present application describes a group III-V device with a rough buffer layer over a silicon substrate, a buffer structure, and a heterojunction structure. The rough buffer layer contains a two-dimensional hole gas (2DHG) due to band bending caused by the buffer structure.
- Rough buffer layer promotes carrier scattering along its surfaces
- Carrier scattering reduces carrier mobility and increases resistance at the 2DHG
- Increased resistance in the silicon substrate reduces substrate losses and increases power added efficiency (PAE)
Potential Applications
- High-efficiency electronic devices
- Power amplifiers
- Photovoltaic cells
Problems Solved
- Reduced substrate losses
- Increased power added efficiency
Benefits
- Improved overall resistance in the silicon substrate
- Enhanced carrier scattering for better performance
- Increased power efficiency
Original Abstract Submitted
Various embodiments of the present application are directed towards a group III-V device including a rough buffer layer. The rough buffer layer overlies a silicon substrate, a buffer structure overlies the rough buffer layer, and a heterojunction structure overlies the buffer structure. The buffer structure causes band bending and formation of a two-dimensional hole gas (2DHG) in the rough buffer layer. The rough buffer layer includes silicon or some other suitable semiconductor material and, in some embodiments, is doped. A top surface of the rough buffer layer and/or a bottom surface of the rough buffer layer is/are rough to promote carrier scattering along the top and bottom surfaces. The carrier scattering reduces carrier mobility and increases resistance at the 2DHG. The increased resistance increases an overall resistance of the silicon substrate, which reduces substrate loses and increases a power added efficiency (PAE).
