18512139. SIDEWALL SPACER STRUCTURE ENCLOSING CONDUCTIVE WIRE SIDEWALLS TO INCREASE RELIABILITY simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)

SIDEWALL SPACER STRUCTURE ENCLOSING CONDUCTIVE WIRE SIDEWALLS TO INCREASE RELIABILITY

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Yu-Teng Dai of New Taipei City (TW)

Chung-Ju Lee of Hsinchu City (TW)

Chih Wei Lu of Hsinchu City (TW)

Hsin-Chieh Yao of Hsinchu City (TW)

Hsi-Wen Tien of Xinfeng Township (TW)

Wei-Hao Liao of Taichung City (TW)

SIDEWALL SPACER STRUCTURE ENCLOSING CONDUCTIVE WIRE SIDEWALLS TO INCREASE RELIABILITY - A simplified explanation of the abstract

This abstract first appeared for US patent application 18512139 titled 'SIDEWALL SPACER STRUCTURE ENCLOSING CONDUCTIVE WIRE SIDEWALLS TO INCREASE RELIABILITY

Simplified Explanation

The integrated chip described in the patent application includes multiple conductive structures on a substrate, separated by a dielectric layer and a spacer structure, with an etch stop layer on top.

• The integrated chip has a plurality of conductive structures on a substrate.
• A first dielectric layer is positioned laterally between the conductive structures.
• A spacer structure is located between the first dielectric layer and the conductive structures.
• An etch stop layer covers the conductive structures and is on the upper surfaces of the spacer structure and the first dielectric layer.

Potential Applications

• Semiconductor manufacturing
• Integrated circuit design
• Electronic device fabrication

Problems Solved

• Improved performance and reliability of integrated chips
• Enhanced protection of conductive structures
• Better control of etching processes

Benefits

• Higher efficiency in chip manufacturing
• Increased durability of integrated chips
• Enhanced functionality of electronic devices

Original Abstract Submitted

Some embodiments relate to an integrated chip including a plurality of conductive structures over a substrate. A first dielectric layer is disposed laterally between the conductive structures. A spacer structure is disposed between the first dielectric layer and the plurality of conductive structures. An etch stop layer overlies the plurality of conductive structures. The etch stop layer is disposed on upper surfaces of the spacer structure and the first dielectric layer.