18511725. MEMORY DEVICE INCLUDING PROCESSING CIRCUIT, AND ELECTRONIC DEVICE INCLUDING SYSTEM ON CHIP AND MEMORY DEVICE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
- 1 MEMORY DEVICE INCLUDING PROCESSING CIRCUIT, AND ELECTRONIC DEVICE INCLUDING SYSTEM ON CHIP AND MEMORY DEVICE
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 MEMORY DEVICE INCLUDING PROCESSING CIRCUIT, AND ELECTRONIC DEVICE INCLUDING SYSTEM ON CHIP AND MEMORY DEVICE - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Original Abstract Submitted
MEMORY DEVICE INCLUDING PROCESSING CIRCUIT, AND ELECTRONIC DEVICE INCLUDING SYSTEM ON CHIP AND MEMORY DEVICE
Organization Name
Inventor(s)
Nam Sung Kim of Yongin-si (KR)
MEMORY DEVICE INCLUDING PROCESSING CIRCUIT, AND ELECTRONIC DEVICE INCLUDING SYSTEM ON CHIP AND MEMORY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18511725 titled 'MEMORY DEVICE INCLUDING PROCESSING CIRCUIT, AND ELECTRONIC DEVICE INCLUDING SYSTEM ON CHIP AND MEMORY DEVICE
Simplified Explanation
The memory device described in the patent application includes a buffer die and a plurality of core dies stacked on top of the buffer die. The core dies each have processing circuits, memory cell arrays, command decoders, and data input/output circuits.
- The buffer die receives broadcast commands from an external device.
- The first core die decodes the first broadcast command and outputs data to a common data bus.
- The second core die decodes the second broadcast command and receives data from the first core die through the common data bus.
Potential Applications
- High-performance computing systems
- Data centers
- Artificial intelligence applications
Problems Solved
- Efficient data transfer between memory devices
- Improved processing speed
- Enhanced memory management
Benefits
- Faster data processing
- Increased efficiency
- Better overall system performance
Original Abstract Submitted
A memory device includes a buffer die configured to receive a first broadcast command and a second broadcast command from an external device; and a plurality of core dies stacked on the buffer die. The plurality of core dies include: a first core die including a first processing circuit, a first memory cell array, a first command decoder configured to decode the first broadcast command, and a first data input/output circuit configured to output data of the first memory cell array to a common data input/output bus under control of the first command decoder; and a second core die including a second processing circuit, a second memory cell array, a second command decoder configured to decode the second broadcast command, and a second data input/output circuit configured to receive the data of the first memory cell array through the common data input/output bus under control of the second command decoder.
