18494164. PIPELINED OUT OF ORDER PAGE MISS HANDLER simplified abstract (Intel Corporation)
Contents
PIPELINED OUT OF ORDER PAGE MISS HANDLER
Organization Name
Inventor(s)
Christopher D. Bryant of Austin TX (US)
PIPELINED OUT OF ORDER PAGE MISS HANDLER - A simplified explanation of the abstract
This abstract first appeared for US patent application 18494164 titled 'PIPELINED OUT OF ORDER PAGE MISS HANDLER
Simplified Explanation
The abstract describes a hardware processor core with a pipelined out-of-order page miss handler circuit.
- The hardware processor core includes an execution circuit, a translation lookaside buffer, and a single page miss handler circuit with multiple pipelined page walk stages.
- The page miss handler circuit can simultaneously handle multiple page walks for different virtual addresses in the translation lookaside buffer.
- The circuit is designed to efficiently handle page misses and translate virtual addresses to physical addresses.
Potential Applications
- High-performance computing systems
- Data centers
- Virtual memory management systems
Problems Solved
- Efficient handling of page misses
- Translation of virtual addresses to physical addresses
- Improving overall system performance
Benefits
- Faster processing of page misses
- Improved system efficiency
- Enhanced performance in handling memory requests
Original Abstract Submitted
Systems, methods, and apparatuses relating to circuitry to implement a pipelined out of order page miss handler are described. In one embodiment, a hardware processor core includes an execution circuit to generate data storage requests for virtual addresses, a translation lookaside buffer to translate the virtual addresses to physical addresses, and a single page miss handler circuit comprising a plurality of pipelined page walk stages, wherein the single page miss handler circuit is to contemporaneously perform a first page walk within a first stage of the plurality of pipelined page walk stages for a first miss of a first virtual address in the translation lookaside buffer, and a second page walk within a second stage of the plurality of pipelined page walk stages for a second miss of a second virtual address in the translation lookaside buffer.
