18457637. GATE DRIVING CIRCUIT, METHOD FOR DRIVING GATE DRIVING CIRCUIT AND DISPLAY PANEL simplified abstract (BOE Technology Group Co., Ltd.)
GATE DRIVING CIRCUIT, METHOD FOR DRIVING GATE DRIVING CIRCUIT AND DISPLAY PANEL
Organization Name
BOE Technology Group Co., Ltd.
Inventor(s)
GATE DRIVING CIRCUIT, METHOD FOR DRIVING GATE DRIVING CIRCUIT AND DISPLAY PANEL - A simplified explanation of the abstract
This abstract first appeared for US patent application 18457637 titled 'GATE DRIVING CIRCUIT, METHOD FOR DRIVING GATE DRIVING CIRCUIT AND DISPLAY PANEL
Simplified Explanation
The abstract describes a gate driving circuit that consists of N stages of cascaded shift registers, divided into at least one group of K stages. Each stage of the shift register is connected to receive a specific clock signal. The input signal terminal of a stage is connected to the output signal terminal of the previous stage, and the reset signal terminals of two consecutive stages are connected to the output signal terminal of a different stage.
- The gate driving circuit includes N stages of cascaded shift registers.
- The shift registers are divided into at least one group of K stages.
- Each stage of the shift register receives a specific clock signal.
- The input signal terminal of a stage is connected to the output signal terminal of the previous stage.
- The reset signal terminals of two consecutive stages are connected to the output signal terminal of a different stage.
Potential Applications:
- Gate driving circuits are commonly used in electronic devices such as displays, power supplies, and motor control systems.
- This technology can be applied in any application that requires precise timing and control of signals.
Problems Solved:
- The gate driving circuit provides a systematic and efficient way to control and synchronize signals in electronic devices.
- It eliminates the need for complex and manual signal routing.
Benefits:
- The cascaded shift registers allow for easy expansion and scalability of the gate driving circuit.
- The specific clock signal assignment ensures accurate and synchronized signal control.
- The connection of input and reset signal terminals simplifies the circuit design and reduces complexity.
Original Abstract Submitted
A gate driving circuit is provided, including N-stages of cascaded shift registers divided into at least one group of K-stages in which a clock signal terminal of a k-th stage of shift register is connected to receive a k-th clock signal, where 1≤k≤K≤N; and an input signal terminal of a n-th stage is connected to an output signal terminal of a (n−i)-th stage, and reset signal terminals of the n-th and (n+1)-th stages are connected to an output signal terminal of a (n+j)-th stage, where 1<n<N, (K−2)/2≤i≤K/2, and K/2<j≤K−2. K=12, the input signal terminal of the n-th stage is connected to an output signal terminal of a (n−6)-th stage, and the reset signal terminals of the n-th stage and the (n+1)-th stage are connected to an output signal terminal of a (n+8)-th stage or a (n+10) stage.
