18455922. SEMICONDUCTOR PACKAGE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Un-Byoung Kang of Suwon-si (KR)
Chung Sun Lee of Suwon-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18455922 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the patent application includes a substrate, a substrate pad, two semiconductor chips, connective terminals, a dummy pad, and an underfill material layer.
- The substrate pad is located on the substrate and serves as a connection point between the substrate and the semiconductor chips.
- The first and second semiconductor chips are positioned on the substrate and connected to the substrate pad via connective terminals.
- A dummy pad is placed on the substrate, separate from the substrate pad, and positioned between the two semiconductor chips.
- An underfill material layer is placed between the substrate and each semiconductor chip to provide support and protection.
Potential applications of this technology:
- Semiconductor packaging for electronic devices
- Integrated circuits in consumer electronics
- Microprocessors in computers and smartphones
Problems solved by this technology:
- Ensures proper connection and support for semiconductor chips
- Reduces the risk of damage during handling and operation
- Improves overall reliability and performance of electronic devices
Benefits of this technology:
- Enhanced durability and longevity of semiconductor packages
- Improved thermal management for semiconductor chips
- Increased efficiency and functionality of electronic devices
Original Abstract Submitted
A semiconductor package includes a substrate; a substrate pad on the substrate; a first semiconductor chip and a second semiconductor chip on the substrate; a connective terminal between the substrate pad and the first semiconductor chip and between the substrate pad and the second semiconductor chip; a dummy pad on the substrate, and spaced apart from the substrate pad, wherein the dummy pad is between the first semiconductor chip and the second semiconductor chip; and an underfill material layer interposed between the substrate and the first semiconductor chip and between the substrate and the second semiconductor chip, wherein the dummy pad and the substrate pad include a same material.
