18448111. INTEGRATED CIRCUIT WITH FEOL RESISTOR simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)
Contents
INTEGRATED CIRCUIT WITH FEOL RESISTOR
Organization Name
Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s)
Tien-Chien Huang of Hsinchu (TW)
Ruey-Bin Sheen of Hsinchu (TW)
Chih-Hsien Chang of Hsinchu (TW)
INTEGRATED CIRCUIT WITH FEOL RESISTOR - A simplified explanation of the abstract
This abstract first appeared for US patent application 18448111 titled 'INTEGRATED CIRCUIT WITH FEOL RESISTOR
Simplified Explanation
The patent application describes a method for forming a semiconductor device with a metal gate structure and a metal resistor structure. Here are the key points:
- The method involves creating a shallow trench isolation (STI) region in a semiconductor substrate to separate an active region and a passive region.
- Sacrificial gate structures are formed over the active and passive regions.
- Source/drain regions are formed in both the active and passive regions.
- The sacrificial gate structures are then replaced with a metal gate structure and a metal resistor structure.
- A gate contact is formed over the metal gate structure, and resistor contacts are formed over the metal resistor structure.
- The metal resistor structure, acting as a dummy gate, is electrically connected to a set of metal lines through the resistor contacts.
Potential applications of this technology:
- Semiconductor devices with improved performance and functionality.
- Integrated circuits with metal gate structures and metal resistor structures.
- Devices requiring precise control of electrical resistance.
Problems solved by this technology:
- Provides a method for forming metal gate structures and metal resistor structures in a semiconductor device.
- Enables the integration of metal lines with the metal resistor structure, allowing for efficient electrical coupling.
Benefits of this technology:
- Enhanced device performance and functionality.
- Improved control over electrical resistance.
- Increased integration capabilities for semiconductor devices.
Original Abstract Submitted
A method includes forming a shallow trench isolation (STI) region in a semiconductor substrate thereby defining an active region and a passive region in the semiconductor substrate and spaced apart from each other by the STI region, forming a first sacrificial gate structure over the active region and a second sacrificial gate structure over the passive region, forming first source/drain regions in the active region and second source/drain regions in the passive region, after forming the first and second source/drain regions, replacing the first sacrificial gate structure with a metal gate structure and the second sacrificial gate structure with a metal resistor structure, the metal resistor structure corresponding to a dummy gate, forming a first gate contact over the metal gate structure, and a pair of resistor contacts over the metal resistor structure, and electrically coupling a set of metal lines with the metal resistor structure by the pair of resistor contacts.
