18403623. SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)
Contents
- 1 SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Sandeep Kumar Goel of Dublin CA (US)
Yun-Han Lee of Boashan Township (TW)
Saman M.I. Adham of Kanata, (CA)
SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS - A simplified explanation of the abstract
This abstract first appeared for US patent application 18403623 titled 'SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS
Simplified Explanation
The patent application describes a device with two dies, each containing a set of latches that are connected to adjacent latches on the same die. The corresponding latches on each die are connected to each other, forming a closed loop scan path. Additionally, one of the latches on the second die is connected to another latch on the same die via an inverter.
- Two dies with sets of latches connected to adjacent latches on the same die
- Corresponding latches on each die are connected to each other, forming a closed loop scan path
- One latch on the second die is connected to another latch on the same die via an inverter
Potential Applications
This technology could be applied in:
- Integrated circuits
- Memory devices
- Logic circuits
Problems Solved
This technology helps in:
- Improving data storage and retrieval efficiency
- Enhancing circuit performance
- Facilitating testing and debugging processes
Benefits
The benefits of this technology include:
- Increased speed and reliability of data processing
- Reduced power consumption
- Simplified design and manufacturing processes
Potential Commercial Applications
The potential commercial applications of this technology include:
- Semiconductor industry
- Electronics manufacturing
- Computer hardware development
Possible Prior Art
One possible prior art for this technology could be:
- Previous patents related to latch-based circuits and scan paths
Unanswered Questions
How does this technology compare to existing latch-based circuits in terms of speed and efficiency?
This article does not provide a direct comparison between this technology and existing latch-based circuits. Further research and testing would be needed to determine the specific advantages of this innovation over current technologies.
What are the potential limitations or drawbacks of implementing this technology in practical applications?
The article does not address any potential limitations or drawbacks of implementing this technology. Additional studies and real-world applications would be necessary to identify any challenges or constraints associated with this innovation.
Original Abstract Submitted
In one embodiment, a device comprises: a first die having disposed thereon a first plurality of latches wherein ones of the first plurality of latches are operatively connected to an adjacent one of the first plurality of latches; and a second die having disposed thereon a second plurality of latches wherein ones of the second plurality of latches are operatively connected to an adjacent one of the second plurality of latches. Each latch of the first plurality of latches on said first die corresponds to a latch in the second plurality of latches on said second die. Each set of corresponding latches are operatively connected. A scan path comprises a closed loop comprising each of said first and second plurality of latches. One of the second plurality of latches is operatively connected to another one of the second plurality of latches via an inverter.
