18403014. RESISTIVE MEMORY CELL WITH SWITCHING LAYER COMPRISING ONE OR MORE DOPANTS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)

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RESISTIVE MEMORY CELL WITH SWITCHING LAYER COMPRISING ONE OR MORE DOPANTS

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Fa-Shen Jiang of Taoyuan City (TW)

Cheng-Yuan Tsai of Chu-Pei City (TW)

Hai-Dang Trinh of Hsinchu (TW)

Hsing-Lien Lin of Hsin-Chu (TW)

Hsun-Chung Kuang of Hsinchu City (TW)

Bi-Shen Lee of Hsin-Chu (TW)

RESISTIVE MEMORY CELL WITH SWITCHING LAYER COMPRISING ONE OR MORE DOPANTS - A simplified explanation of the abstract

This abstract first appeared for US patent application 18403014 titled 'RESISTIVE MEMORY CELL WITH SWITCHING LAYER COMPRISING ONE OR MORE DOPANTS

Simplified Explanation

The integrated chip described in the patent application includes a first conductive structure, a data storage structure, and a second conductive structure. The data storage structure consists of two dielectric layers with a dopant that changes in concentration from the top surface towards the first conductive structure.

  • The integrated chip includes a first conductive structure over a substrate.
  • A data storage structure is positioned over the first conductive structure, comprising two dielectric layers with a changing dopant concentration.
  • A second conductive structure is located above the data storage structure.

Potential Applications

This technology could be used in:

  • Memory storage devices
  • Semiconductor manufacturing

Problems Solved

This technology addresses:

  • Improving data storage efficiency
  • Enhancing semiconductor performance

Benefits

The benefits of this technology include:

  • Increased data storage capacity
  • Enhanced semiconductor functionality

Potential Commercial Applications

This technology could be applied in:

  • Consumer electronics
  • Data centers

Possible Prior Art

One possible prior art for this technology could be:

  • Memory devices with multiple dielectric layers

Unanswered Questions

How does this technology impact energy consumption in electronic devices?

This article does not provide information on the energy efficiency of the integrated chip described.

What are the potential limitations of this technology in terms of scalability?

The article does not discuss the scalability of this integrated chip technology.


Original Abstract Submitted

Various embodiments of the present disclosure are directed towards an integrated chip including a first conductive structure over a substrate. A data storage structure overlies the first conductive structure. The data storage structure comprises a first dielectric layer on the first conductive structure and a second dielectric layer on the first dielectric layer. The first dielectric layer comprises a dielectric material and a first dopant having a concentration that changes from a top surface of the first dielectric layer in a direction towards the first conductive structure. A second conductive structure overlies the data storage structure.