18401988. THREE-DIMENSIONAL MEMORY DEVICE AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)

THREE-DIMENSIONAL MEMORY DEVICE AND METHOD

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Feng-Cheng Yang of Zhudong Township (TW)

Meng-Han Lin of Hsinchu (TW)

Sheng-Chen Wang of Hsinchu (TW)

Han-Jong Chia of Hsinchu (TW)

Chung-Te Lin of Tainan City (TW)

THREE-DIMENSIONAL MEMORY DEVICE AND METHOD - A simplified explanation of the abstract

This abstract first appeared for US patent application 18401988 titled 'THREE-DIMENSIONAL MEMORY DEVICE AND METHOD

Simplified Explanation

The abstract describes a patent application for a memory array formed using a multiple patterning process. The process involves creating trenches within a multiple layer stack, depositing conductive materials into the trenches, and etching the materials to form the memory array.

• Formation of memory array using multiple patterning process:

 - Involves creating trenches within a multiple layer stack.
 - Depositing first conductive material into the first trench.
 - Forming a second trench and depositing a second conductive material.
 - Etching the first and second conductive materials.

Potential Applications

The technology described in this patent application could be applied in the manufacturing of memory devices, such as DRAM or NAND flash memory, where high-density memory arrays are required.

Problems Solved

This technology solves the problem of increasing memory density in semiconductor devices by utilizing a multiple patterning process to form memory arrays with smaller feature sizes and higher storage capacity.

Benefits

The benefits of this technology include: - Higher memory density. - Improved performance of memory devices. - Enhanced storage capacity in semiconductor devices.

Potential Commercial Applications

"Memory Array Formation Using Multiple Patterning Process" could find commercial applications in the semiconductor industry for the production of advanced memory devices with increased storage capacity and improved performance.

Possible Prior Art

One possible prior art related to this technology is the use of multiple patterning processes in semiconductor manufacturing to achieve higher resolution and smaller feature sizes in memory arrays.

How does this technology compare to existing memory array formation processes?

This article does not provide a direct comparison between the technology described and existing memory array formation processes. It would be helpful to understand the specific advantages and disadvantages of this approach compared to traditional methods.

What are the potential challenges in scaling up this technology for mass production?

The article does not address the potential challenges in scaling up this technology for mass production. It would be important to consider factors such as cost, scalability, and compatibility with existing manufacturing processes.

Original Abstract Submitted

In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.