18400749. ANALOG MAC AWARE DNN IMPROVEMENT simplified abstract (Microsoft Technology Licensing, LLC)
Contents
- 1 ANALOG MAC AWARE DNN IMPROVEMENT
ANALOG MAC AWARE DNN IMPROVEMENT
Organization Name
Microsoft Technology Licensing, LLC
Inventor(s)
Gilad Kirshenboim of Petach Tiqva (IL)
Douglas C. Burger of Bellevue WA (US)
Yehonathan Refael Kalim of Herzeliya (IL)
ANALOG MAC AWARE DNN IMPROVEMENT - A simplified explanation of the abstract
This abstract first appeared for US patent application 18400749 titled 'ANALOG MAC AWARE DNN IMPROVEMENT
Simplified Explanation
The patent application discusses methods to improve the performance of a hardware accelerator, such as a neural processor, by selectively varying the precision of multiply and accumulate processing elements (MAC PEs) to reduce power consumption. Dynamic control of analog to digital output bits for MAC PEs based on precision information from training and post-training of an artificial intelligence neural network model is also described.
- Selective variation of MAC PE precision to reduce power consumption
- Dynamic control of ADC output bit precision based on AI NN model precision information
Potential Applications
The technology described in the patent application could be applied in various fields such as artificial intelligence, machine learning, robotics, autonomous vehicles, and data centers.
Problems Solved
The technology addresses the issue of power consumption in hardware accelerators, specifically neural processors, by dynamically controlling the precision of MAC PEs based on the requirements of the AI neural network model.
Benefits
- Improved performance of hardware accelerators - Reduced power consumption - Enhanced efficiency in AI neural network processing
Potential Commercial Applications
The technology could be utilized in the development of energy-efficient neural processors for applications in AI, machine learning, and other computational tasks.
Possible Prior Art
One possible prior art could be the use of fixed precision MAC PEs in hardware accelerators, which may not offer the same level of power optimization as the dynamic precision control described in the patent application.
Unanswered Questions
How does the dynamic precision control impact the overall performance of the neural processor?
The patent application discusses the power-saving benefits of dynamically controlling the precision of MAC PEs, but it does not delve into how this may affect the speed or accuracy of the neural processor.
Are there any potential drawbacks or limitations to implementing dynamic precision control in hardware accelerators?
While the patent application highlights the advantages of dynamic precision control, it does not address any potential challenges or constraints that may arise from implementing this technology.
Original Abstract Submitted
Methods, systems and computer program products are provided for improving performance (e.g., reducing power consumption) of a hardware accelerator (e.g., neural processor) comprising hybrid or analog multiply and accumulate (MAC) processing elements (PEs). Selective variation of the precision of an array of MAC PEs may reduce power consumption of a neural processor. Power may be conserved by dynamically controlling the precision of analog to digital (ADC) output bits for one or more MAC PEs. Dynamic control of ADC output bit precision may be based on precision information determined during training and/or post-training (e.g., quantization) of an artificial intelligence (AI) neural network (NN) model implemented by the neural processor. Precision information may include a range of dynamic precision for each of a plurality of nodes of a computation graph for the AI NN model.
