18399381. FLOATING-POINT DECOMPOSITION CIRCUITRY WITH DYNAMIC PRECISION simplified abstract (Intel Corporation)
Contents
- 1 FLOATING-POINT DECOMPOSITION CIRCUITRY WITH DYNAMIC PRECISION
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 FLOATING-POINT DECOMPOSITION CIRCUITRY WITH DYNAMIC PRECISION - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
FLOATING-POINT DECOMPOSITION CIRCUITRY WITH DYNAMIC PRECISION
Organization Name
Inventor(s)
Roberto Dicecco of Toronto (CA)
Joshua Fender of East York (CA)
Shane O'connell of Toronto (CA)
FLOATING-POINT DECOMPOSITION CIRCUITRY WITH DYNAMIC PRECISION - A simplified explanation of the abstract
This abstract first appeared for US patent application 18399381 titled 'FLOATING-POINT DECOMPOSITION CIRCUITRY WITH DYNAMIC PRECISION
Simplified Explanation
The circuitry described in the patent application is designed to decompose block floating-point numbers into lower precision floating-point numbers by utilizing high precision storage circuit, input selectors, and a low precision block floating-point vector circuit. The input selectors adjust the exponents of the high precision floating-point numbers to generate corresponding lower precision floating-point components, which are then combined by the low precision block floating-point vector circuit.
- High precision storage circuit for providing high precision floating-point numbers
- Input selectors for generating lower precision floating-point components with adjusted exponents
- Low precision block floating-point vector circuit for combining the lower precision floating-point components
- Spatial or iterative processing of the lower precision floating-point components
Potential Applications
This technology could be applied in signal processing, image processing, scientific computing, and machine learning algorithms that require efficient handling of floating-point numbers.
Problems Solved
This technology solves the problem of efficiently decomposing high precision floating-point numbers into lower precision components without losing significant accuracy.
Benefits
The benefits of this technology include improved efficiency in processing high precision floating-point numbers, reduced computational complexity, and potential energy savings in computing systems.
Potential Commercial Applications
Potential commercial applications of this technology include high-performance computing systems, data centers, scientific research facilities, and artificial intelligence hardware accelerators.
Possible Prior Art
One possible prior art for this technology could be the use of fixed-point arithmetic or traditional floating-point decomposition methods in computing systems.
Unanswered Questions
How does this technology compare to existing methods for decomposing floating-point numbers?
This article does not provide a direct comparison between this technology and existing methods for decomposing floating-point numbers.
What are the limitations of this circuitry in terms of precision and speed?
The article does not address the potential limitations of this circuitry in terms of precision and speed.
Original Abstract Submitted
Circuitry for decomposing block floating-point numbers into lower precision floating-point numbers is provided. The circuitry may include a high precision storage circuit configured to provide high precision floating-point numbers, input selectors configured to receive the high precision floating-point numbers from the high precision storage circuit and to generate corresponding lower precision floating-point components with adjusted exponents, and a low precision block floating-point vector circuit configured to combine the various lower precision floating-point components generated by the input selectors. The lower precision floating-point components may be processed spatially or over multiple iterations over time.
