18399189. NO MOLD SHELF PACKAGE DESIGN AND PROCESS FLOW FOR ADVANCED PACKAGE ARCHITECTURES simplified abstract (Intel Corporation)

NO MOLD SHELF PACKAGE DESIGN AND PROCESS FLOW FOR ADVANCED PACKAGE ARCHITECTURES

Organization Name

Intel Corporation

Inventor(s)

Wei Li of Chandler AZ (US)

Edvin Cetegen of Chandler AZ (US)

Nicholas S. Haehn of Scottsdale AZ (US)

Ram S. Viswanath of Phoenix AZ (US)

Nicholas Neal of Gilbert AZ (US)

Mitul Modi of Phoenix AZ (US)

NO MOLD SHELF PACKAGE DESIGN AND PROCESS FLOW FOR ADVANCED PACKAGE ARCHITECTURES - A simplified explanation of the abstract

This abstract first appeared for US patent application 18399189 titled 'NO MOLD SHELF PACKAGE DESIGN AND PROCESS FLOW FOR ADVANCED PACKAGE ARCHITECTURES

Simplified Explanation

The semiconductor package described in the patent application includes a substrate with a plurality of dies and an encapsulation layer surrounding the dies. Additionally, there are dummy silicon regions on the substrate that surround the dies and encapsulation layer. These dummy silicon regions are positioned on two or more edges of the substrate and have a top surface that is substantially coplanar to the top surface of the dies. The dummy silicon regions are made of materials with high thermal conductivity, such as silicon, metals, or highly thermally conductive materials.

• Substrate with dies and encapsulation layer
• Dummy silicon regions on substrate surrounding dies and encapsulation layer
• Dummy silicon regions positioned on edges of substrate
• Dummy silicon regions made of materials with high thermal conductivity

Potential Applications

The technology described in the patent application could be applied in various semiconductor packaging applications where thermal management is crucial, such as in high-performance computing, automotive electronics, and industrial control systems.

Problems Solved

This technology helps in improving thermal management in semiconductor packages by providing dummy silicon regions with high thermal conductivity, which helps in dissipating heat efficiently and preventing overheating of the dies.

Benefits

- Enhanced thermal management - Improved reliability and longevity of semiconductor packages - Better performance under high temperature conditions

Potential Commercial Applications

"High Thermal Conductivity Semiconductor Packages for Enhanced Thermal Management"

Possible Prior Art

There are existing semiconductor packaging technologies that use dummy silicon regions for thermal management, but the specific combination of materials with high thermal conductivity as described in this patent application may be a novel approach.

Unanswered Questions

1. What specific manufacturing processes are used to create the dummy silicon regions with high thermal conductivity? 2. How does the presence of dummy silicon regions impact the overall cost of manufacturing semiconductor packages?

Original Abstract Submitted

Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.