18396335. SUPER-OPTIMIZATION EXPLORER USING E-GRAPH REWRITING FOR HIGH-LEVEL SYNTHESIS simplified abstract (Intel Corporation)
Contents
- 1 SUPER-OPTIMIZATION EXPLORER USING E-GRAPH REWRITING FOR HIGH-LEVEL SYNTHESIS
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 SUPER-OPTIMIZATION EXPLORER USING E-GRAPH REWRITING FOR HIGH-LEVEL SYNTHESIS - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
SUPER-OPTIMIZATION EXPLORER USING E-GRAPH REWRITING FOR HIGH-LEVEL SYNTHESIS
Organization Name
Inventor(s)
Lorenzo Chelini of Zurich (CH)
Rafael Barbalho of Orangevale CA (US)
Theo Drane of El Dorado Hills CA (US)
SUPER-OPTIMIZATION EXPLORER USING E-GRAPH REWRITING FOR HIGH-LEVEL SYNTHESIS - A simplified explanation of the abstract
This abstract first appeared for US patent application 18396335 titled 'SUPER-OPTIMIZATION EXPLORER USING E-GRAPH REWRITING FOR HIGH-LEVEL SYNTHESIS
Simplified Explanation
The technique described in the patent application is for automatic program code optimization for high-level synthesis. It involves translating program code from a high-level language into an intermediate language, constructing an equality graph (e-graph) from the intermediate language, exploring equivalent hardware designs through various transformations, selecting a hardware design based on a cost function, and generating program code in the high-level language for high-level synthesis.
- Translation of program code: The method involves translating the first program code in a high-level language into an intermediate language.
- Construction of e-graph: An equality graph (e-graph) is constructed from the intermediate language to represent equivalent hardware designs.
- Transformation exploration: Control-flow, data path, and gate-level transformations are interleaved to explore different hardware design options.
- Hardware design selection: A hardware design is selected based on a cost function.
- Program code generation: A representation of the selected hardware design is extracted in the intermediate language, and second program code in the high-level language is generated for high-level synthesis.
Potential Applications
This technology can be applied in the field of electronic design automation (EDA) for optimizing program code for high-level synthesis, leading to more efficient hardware designs.
Problems Solved
This technology solves the problem of manual optimization of program code for high-level synthesis, automating the process to explore and select the best hardware design based on a cost function.
Benefits
The benefits of this technology include improved efficiency in hardware design, reduced development time, and optimized utilization of resources for high-level synthesis.
Potential Commercial Applications
A potential commercial application of this technology is in the semiconductor industry for developing optimized hardware designs through high-level synthesis.
Possible Prior Art
One possible prior art in this field is the use of constraint-based synthesis techniques for optimizing hardware designs in electronic design automation.
Original Abstract Submitted
Described herein is a technique for automatic program code optimization for high-level synthesis. One embodiment provides a method comprising receiving input including first program code in a high-level language; translating the first program code into an intermediate language; constructing an equality graph (e-graph) from the intermediate language; interleaving control-flow, data path, and gate-level transformations to explore equivalent hardware designs represented by the e-graph; selecting a hardware design based on a cost function; extracting a representation of a selected hardware design in the intermediate language; generating second program code in the high-level language; and performing high-level synthesis using the second program code.
