18380691. METHOD OF MEASURING OVERLAY OFFSET AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
- 1 METHOD OF MEASURING OVERLAY OFFSET AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 METHOD OF MEASURING OVERLAY OFFSET AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
METHOD OF MEASURING OVERLAY OFFSET AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME
Organization Name
Inventor(s)
Seunghak Park of Suwon-si (KR)
METHOD OF MEASURING OVERLAY OFFSET AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18380691 titled 'METHOD OF MEASURING OVERLAY OFFSET AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME
Simplified Explanation
The method described in the abstract involves measuring an overlay offset between two patterns on a substrate using Zernike polynomial modeling. The process includes acquiring overlay information, detecting the overlay offset, and obtaining compensation overlay information.
- Providing a substrate with lower and upper patterns
- Acquiring overlay information about the positions of the patterns
- Detecting overlay offset through Zernike polynomial modeling
- Acquiring compensation overlay information based on the overlay offset, including radial tilting component
Potential Applications
This technology could be applied in the semiconductor industry for improving the accuracy of overlay measurements in the manufacturing process of integrated circuits.
Problems Solved
This technology helps in accurately measuring overlay offsets between different patterns on a substrate, which is crucial for ensuring the quality and performance of semiconductor devices.
Benefits
- Enhanced accuracy in measuring overlay offsets - Improved quality control in semiconductor manufacturing - Increased efficiency in the production of integrated circuits
Potential Commercial Applications
"Improving Overlay Offset Measurement in Semiconductor Manufacturing"
Possible Prior Art
One possible prior art in this field could be the use of image processing techniques for overlay measurement in semiconductor manufacturing processes.
What are the limitations of the current method?
The abstract does not mention any limitations of the current method.
How does this method compare to existing overlay measurement techniques?
The abstract does not provide a comparison of this method with existing overlay measurement techniques.
Original Abstract Submitted
A method of measuring an overlay offset, the method includes: providing a substrate including a lower pattern and an upper pattern, wherein the lower pattern is disposed in a cell area, and the upper pattern is disposed on the lower pattern; acquiring a first piece of overlay information about a first position of the lower pattern and a second position of the upper pattern by detecting a pupil image of a joint position that is between the upper pattern and the lower pattern; detecting an overlay offset of the second position of the upper pattern relative to the first position of the lower pattern through Zernike polynomial modeling; and acquiring compensation overlay information on the upper pattern from the overlay offset of the second position, wherein the overlay offset includes a radial tilting component.
