18374437. SEMICONDUCTOR PACKAGE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
- 1 SEMICONDUCTOR PACKAGE
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 How does this technology compare to traditional semiconductor packaging methods?
- 1.11 What are the specific manufacturing processes involved in implementing this technology?
- 1.12 Original Abstract Submitted
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18374437 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the abstract includes a first substrate with a substrate pad, a first chip stacked structure with multiple chips connected by wires, and a second chip stacked structure with chips offset-stacked from the first chip structure. The lowermost chip in the second structure is positioned higher vertically than the highest level of the lowermost wire in the first structure.
- First substrate with upper and lower surfaces
- Substrate pad on upper surface
- First chip stack with multiple chips stacked in a first direction
- Lowermost wire connecting lowermost chip to substrate pad
- Second chip stack with chips offset-stacked from first chip stack
- Lowermost chip in second stack positioned higher vertically than highest level of lowermost wire
Potential Applications
The technology described in this patent application could be used in various semiconductor devices, such as microprocessors, memory chips, and integrated circuits.
Problems Solved
This technology allows for more efficient stacking of chips in a semiconductor package, reducing the overall size of the package while maintaining electrical connections between the chips.
Benefits
The benefits of this technology include increased packaging density, improved thermal performance, and potentially lower manufacturing costs due to the compact design.
Potential Commercial Applications
One potential commercial application of this technology could be in the development of smaller and more powerful mobile devices, such as smartphones and tablets, where space is limited but performance is crucial.
Possible Prior Art
One possible prior art for this technology could be the use of stacked chip structures in semiconductor packages, but the specific arrangement and spacing described in this patent application may be novel and innovative.
Unanswered Questions
How does this technology compare to traditional semiconductor packaging methods?
This article does not provide a direct comparison between this technology and traditional semiconductor packaging methods in terms of performance, cost, or efficiency.
What are the specific manufacturing processes involved in implementing this technology?
The article does not detail the specific manufacturing processes or techniques required to produce semiconductor packages using this technology.
Original Abstract Submitted
Provided is a semiconductor package including a first substrate having an upper surface and a lower surface, and including a substrate pad arranged on the upper surface, a first chip stacked structure mounted on the upper surface of the first substrate, and including a plurality of first chips offset-stacked in a first direction, a lowermost first wire electrically connecting a lowermost first chip to the substrate pad, and a second chip stacked structure mounted on the upper surface of the first substrate, and including a plurality of second chips offset-stacked in the first direction, wherein the second chip stacked structure is spaced apart from the first chip stacked structure with the lowermost first wire therebetween in a horizontal direction, and an upper surface of a lowermost second chip is at a higher vertical direction level than a highest level of the lowermost first wire in a vertical direction.
