18369082. FREQUENCY SCALING FOR PER-CORE ACCELERATOR ASSIGNMENTS simplified abstract (Intel Corporation)

FREQUENCY SCALING FOR PER-CORE ACCELERATOR ASSIGNMENTS

Organization Name

Intel Corporation

Inventor(s)

Stephen T. Palermo of Chandler AZ (US)

Srihari Makineni of Portland OR (US)

Shubha Bommalingaiahnapallya of East Brunswick NJ (US)

Neelam Chandwani of Portland OR (US)

Rany T. Elsayed of Folsom CA (US)

Udayan Mukherjee of Portland OR (US)

Lokpraveen Mosur of Gilbert AZ (US)

Adwait Purandare of Beaverton OR (US)

FREQUENCY SCALING FOR PER-CORE ACCELERATOR ASSIGNMENTS - A simplified explanation of the abstract

This abstract first appeared for US patent application 18369082 titled 'FREQUENCY SCALING FOR PER-CORE ACCELERATOR ASSIGNMENTS

Simplified Explanation

The patent application describes methods for frequency scaling for per-core accelerator assignments in a processor with multiple cores. Some cores can be configured to support advanced AVX/AMX instructions, while others are configured to not support these instructions. This allows for enhanced performance and flexibility in handling various workloads.

• Selective configuration of CPU cores to support frequency scaling and instruction extensions
• Some cores support AVX/AMX instructions, while others do not
• AVX/AMX instructions implemented in separate ISA extension units
• Cores with disabled units consume less power and operate at higher frequencies
• Enhanced performance and flexibility in handling advanced workloads

Potential Applications

This technology can be applied in high-performance computing, artificial intelligence, machine learning, and data analytics where advanced AVX/AMX instructions are required for accelerated workloads.

Problems Solved

This technology solves the problem of power consumption and frequency limitations in processors when supporting advanced AVX/AMX instructions. It also provides flexibility in handling different types of workloads efficiently.

Benefits

The benefits of this technology include improved performance, reduced power consumption, increased flexibility in workload management, and support for advanced instruction sets.

Potential Commercial Applications

Potential commercial applications of this technology include server processors, data centers, supercomputers, AI accelerators, and other high-performance computing systems.

Possible Prior Art

One possible prior art could be the use of dynamic voltage and frequency scaling (DVFS) techniques in processors to optimize power consumption and performance based on workload requirements. Another could be the use of heterogeneous computing architectures to offload specific tasks to specialized accelerators for improved efficiency.

Unanswered Questions

How does this technology impact overall system cost?

The patent application does not provide information on the potential cost implications of implementing this technology. It would be important to understand if there are any additional costs associated with integrating separate ISA extension units in CPU cores.

Are there any limitations to the scalability of this technology?

The scalability of this technology in terms of the number of cores and the complexity of workloads that can be efficiently handled is not discussed in the patent application. It would be interesting to know if there are any limitations to scaling this approach to larger processor configurations.

Original Abstract Submitted

Methods for frequency scaling for per-core accelerator assignments and associated apparatus. A processor includes a CPU (central processing unit) having multiple cores that can be selectively configured to support frequency scaling and instruction extensions. Under this approach, some cores can be configured to support a selective set of AVX instructions (such as AVX3/5G-ISA instructions) and/or AMX instructions, while other cores are configured to not support these AVX/AMX instructions. In one aspect, the selective AVX/AMX instructions are implemented in one or more ISA extension units that are separate from the main processor core (or otherwise comprises a separate block of circuitry in a processor core) that can be selectively enabled or disabled. This enables cores having the separate unit(s) disabled to consume less power and/or operate at higher frequencies, while supporting the selective AVX/AMX instructions using other cores. These capabilities enhance performance and provides flexibility to handle a variety of applications requiring use of advanced AVX/AMX instructions to support accelerated workloads.