18362842. PIN ACCESS HYBRID CELL HEIGHT DESIGN AND SYSTEM simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

PIN ACCESS HYBRID CELL HEIGHT DESIGN AND SYSTEM

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Kam-Tou Sio of Hsinchu (TW)

Jiann-Tyng Tzeng of Hsinchu (TW)

PIN ACCESS HYBRID CELL HEIGHT DESIGN AND SYSTEM - A simplified explanation of the abstract

This abstract first appeared for US patent application 18362842 titled 'PIN ACCESS HYBRID CELL HEIGHT DESIGN AND SYSTEM

Simplified Explanation

The abstract describes a method for generating a layout diagram for an integrated circuit. The method involves arranging multiple cells in the layout diagram, where each cell has power rails along its boundaries. The cells are placed in a specific direction, and cell pins are positioned over selected via placement points in one of the cells, following a design rule. The cell pins have one end spaced from both power rails in the specified direction.

• The method involves arranging cells in a layout diagram for an integrated circuit.
• Each cell in the layout diagram has power rails along its boundaries.
• The cells are placed in a specific direction, with one boundary spaced from the other boundary.
• Cell pins are positioned over selected via placement points in one of the cells.
• The placement of cell pins follows a design rule.
• The cell pins have one end spaced from both power rails in the specified direction.

Potential Applications

• This method can be used in the design and layout of integrated circuits.
• It can be applied in various industries that utilize integrated circuits, such as electronics, telecommunications, and computing.

Problems Solved

• The method provides a systematic approach to generating layout diagrams for integrated circuits.
• It ensures proper placement of cells and cell pins, following design rules.
• The method helps in optimizing the layout for efficient power distribution and signal routing.

Benefits

• The method allows for the efficient arrangement of cells in an integrated circuit layout.
• It ensures proper spacing between power rails and cell pins, reducing the risk of electrical interference.
• The systematic approach helps in improving the overall performance and reliability of the integrated circuit.

Original Abstract Submitted

A method of generating a layout diagram for an integrated circuit includes arranging a plurality of cells in the layout diagram, wherein each cell of the plurality of cells comprises a first power rail along a first boundary and a second power rail along a second boundary, and the first boundary is spaced from the second boundary in a first direction. The method further includes placing a plurality of cell pins over a plurality of selected via placement points in a first cell of the plurality of cells in accordance with a design rule, wherein a first cell pin of the plurality of cell pins has a first end spaced from both the first power rail and the second power rail in the first direction.