18359031. SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE simplified abstract (Samsung Electronics Co., Ltd.)

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SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE

Organization Name

Samsung Electronics Co., Ltd.

Inventor(s)

Hyoeun Kim of Suwon-si (KR)

Dohyun Kim of Suwon-si (KR)

Sunkyoung Seo of Suwon-si (KR)

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18359031 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE

Simplified Explanation

The semiconductor package described in the abstract includes two semiconductor chips bonded directly to each other, with wiring layers and passivation layers exposed to allow for bonding of bonding pads and test pads.

  • The semiconductor package consists of a first semiconductor chip with a first wiring layer and passivation layer, and a second semiconductor chip with a second wiring layer and passivation layer.
  • The first and second chips are directly bonded to each other, with bonding pads and test pads exposed on the wiring layers for connection.
  • The direct bonding of the passivation layers ensures a secure connection between the two chips.

Potential Applications

This technology could be applied in the manufacturing of advanced semiconductor devices, such as integrated circuits and microprocessors, where multiple chips need to be stacked and interconnected.

Problems Solved

This technology solves the problem of efficiently connecting multiple semiconductor chips in a compact package, while ensuring reliable electrical connections between the chips.

Benefits

The direct bonding of the chips and passivation layers simplifies the packaging process, reduces the overall size of the semiconductor package, and improves the reliability of the connections between the chips.

Potential Commercial Applications

One potential commercial application of this technology could be in the development of high-performance computing devices, where compact and reliable semiconductor packaging is essential for optimal performance.

Possible Prior Art

One possible prior art for this technology could be the use of flip-chip bonding techniques in semiconductor packaging, where chips are directly bonded to each other to improve electrical connections and reduce package size.

Unanswered Questions

How does this technology compare to traditional wire bonding techniques in semiconductor packaging?

This article does not provide a direct comparison between this technology and traditional wire bonding techniques in semiconductor packaging.

What are the potential challenges in scaling up this technology for mass production?

This article does not address the potential challenges in scaling up this technology for mass production.


Original Abstract Submitted

A semiconductor package includes a first semiconductor chip and a second semiconductor chip on the first semiconductor chip. The first semiconductor chip includes a first wiring layer on a first substrate, and a first passivation layer on the first wiring layer and that exposes at least portions of first bonding pads and a first test pad that are on the second wiring layer. The second semiconductor chip includes a second wiring layer on a second substrate and a second passivation layer on the second wiring layer and that exposes at least portions of third bonding pads and second test pad that are provided on the second wiring layer. The first bonding pads and respective ones of the third bonding pads are directly bonded to each other. The first passivation layer and the second passivation layer are directly bonded to each other.