18356682. SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

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SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING THE SAME

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Seokgeun Ahn of Suwon-si (KR)

Daewoo Kim of Suwon-si (KR)

Seokhyun Lee of Suwon-si (KR)

SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 18356682 titled 'SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING THE SAME

Simplified Explanation

The semiconductor package described in the abstract includes a first redistribution wiring layer with two surfaces, a connection layer, two semiconductor chips mounted on the connection layer, a molding member covering the chips, and a second redistribution wiring layer on top of the molding member.

  • The first redistribution wiring layer has a first chip mounting region and a second chip mounting region.
  • The connection layer is located on the first surface of the first redistribution wiring layer.
  • The first semiconductor chip is mounted on the first chip mounting region.
  • The second semiconductor chip is placed on the second chip mounting region and has through electrodes.
  • The molding member covers both semiconductor chips.
  • The second redistribution wiring layer is electrically connected to the first redistribution wiring layer through the through electrodes.

Potential Applications

This technology could be applied in:

  • Advanced electronic devices
  • Semiconductor manufacturing industry

Problems Solved

This technology helps in:

  • Improving electrical connections in semiconductor packages
  • Enhancing the performance of semiconductor chips

Benefits

The benefits of this technology include:

  • Increased efficiency in electronic devices
  • Enhanced reliability of semiconductor packages

Potential Commercial Applications

The potential commercial applications of this technology could be in:

  • Consumer electronics
  • Telecommunications industry

Possible Prior Art

One possible prior art for this technology could be the use of redistribution wiring layers in semiconductor packages to improve electrical connections.

Unanswered Questions

How does this technology compare to traditional semiconductor packaging methods?

This article does not provide a direct comparison between this technology and traditional semiconductor packaging methods.

What are the specific materials used in the construction of this semiconductor package?

The article does not mention the specific materials used in the construction of this semiconductor package.


Original Abstract Submitted

A semiconductor package, comprising: a first redistribution wiring layer including first and second surfaces opposite to each other, wherein the first redistribution wiring layer includes a first chip mounting region and a second chip mounting region adjacent to the first chip mounting region; a connection layer on the first surface of the first redistribution wiring layer; a first semiconductor chip on the first chip mounting region on the connection layer; a second semiconductor chip spaced apart from the first semiconductor chip on the second chip mounting region on the connection layer, wherein the second semiconductor chip includes through electrodes; a molding member on the first and second semiconductor chips on the connection layer; and a second redistribution wiring layer on the molding member, wherein the second redistribution wiring layer is electrically connected to the first redistribution wiring layer through the through electrodes.