18351629. Global Boosting Circuit simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)
Contents
Global Boosting Circuit
Organization Name
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s)
Global Boosting Circuit - A simplified explanation of the abstract
This abstract first appeared for US patent application 18351629 titled 'Global Boosting Circuit
Simplified Explanation
The patent application describes a memory device with a first memory array, a local input/output (LIO) circuit, and a global input/output (GIO) circuit.
- The first memory array includes a memory cell and a local bit line.
- The LIO circuit receives a local bit line signal and generates a global bit line signal based on it.
- The GIO circuit is connected to the LIO circuit and receives the global bit line signal.
- The GIO circuit includes a latch circuit with a global bit line signal latch and a booster circuit to drive the global bit line signal based on a previous signal.
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- Potential Applications
- This technology can be used in various memory devices such as RAM, flash memory, and solid-state drives.
- It can also be applied in data storage systems, embedded systems, and computing devices.
- Problems Solved
- Improves data transfer efficiency and speed within memory devices.
- Enhances the reliability and performance of memory arrays.
- Reduces power consumption and heat generation in memory devices.
- Benefits
- Faster data transfer rates between memory cells.
- Increased reliability and stability of memory devices.
- Lower power consumption and improved energy efficiency.
- Enhanced overall performance of memory arrays.
Original Abstract Submitted
Systems and methods are provided for a memory device including a first memory array, a local input/output (LIO) circuit, and a global input/output (GIO) circuit. The first memory array includes a memory cell and a local bit line. The LIO circuit is configured to receive a local bit line signal on the local bit line and to generate a global bit line signal on a global bit line based on the local bit line signal. The GIO circuit is coupled to the LIO circuit and is configured to receive the global bit line signal. The GIO circuit comprises a latch circuit including a global bit line signal latch that is configured to latch the global bit line signal, and a booster circuit that is configured to drive the global bit line signal in the GIO circuit based on a previous global bit line signal.
