18348591. SEMICONDUCTOR PACKAGE INCLUDING MEMORY DIE STACK HAVING CLOCK SIGNAL SHARED BY LOWER AND UPPER BYTES simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
SEMICONDUCTOR PACKAGE INCLUDING MEMORY DIE STACK HAVING CLOCK SIGNAL SHARED BY LOWER AND UPPER BYTES
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SEMICONDUCTOR PACKAGE INCLUDING MEMORY DIE STACK HAVING CLOCK SIGNAL SHARED BY LOWER AND UPPER BYTES - A simplified explanation of the abstract
This abstract first appeared for US patent application 18348591 titled 'SEMICONDUCTOR PACKAGE INCLUDING MEMORY DIE STACK HAVING CLOCK SIGNAL SHARED BY LOWER AND UPPER BYTES
Simplified Explanation
The abstract describes a semiconductor package that includes a memory die stack with a shared clock signal for lower and upper bytes. Each memory die in the stack has a clock circuit that generates a read clock signal for the lower and upper bytes. The package also has multiple die bond pads corresponding to the number of ranks in a memory system, with each bond pad set for each rank. The clock circuit is connected to a die bond pad that corresponds to the rank of the memory die.
- The semiconductor package includes a memory die stack with a shared clock signal for lower and upper bytes.
- Each memory die in the stack has a clock circuit that generates a read clock signal for the lower and upper bytes.
- The package has multiple die bond pads corresponding to the number of ranks in a memory system.
- Each die bond pad is set for each rank.
- The clock circuit is connected to a die bond pad that corresponds to the rank of the memory die.
Potential applications of this technology:
- Memory systems in various electronic devices such as computers, smartphones, and tablets.
- Data storage devices that require efficient clock signal sharing between lower and upper bytes.
Problems solved by this technology:
- Efficient sharing of clock signals between lower and upper bytes in a memory die stack.
- Simplified design and implementation of clock circuits in memory dies.
Benefits of this technology:
- Improved performance and reliability of memory systems.
- Reduced complexity and cost of memory die stack designs.
- Enhanced data transfer speed and efficiency.
Original Abstract Submitted
A semiconductor package includes a memory die stack having a clock signal shared by lower and upper bytes. Each of a plurality of memory dies constituting the memory die stack of the semiconductor package includes a first clock circuit configured to generate a read clock signal for a lower byte and an upper byte constituting a data width of the memory die, and a plurality of first die bond pads corresponding to the number of ranks of a memory system including the memory die, and each of the plurality of first die bond pads is set for each rank. The first clock circuit is connected to, among the plurality of first die bond pads, a die bond pad corresponding to a rank to which the memory die belongs.
