18345955. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18345955 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the patent application includes a redistribution structure with multiple redistribution layers, a semiconductor chip placed on one surface of the structure, a frame with a wiring structure connected to a redistribution via, and UBM layers with UBM vias on the other surface of the structure. The UBM layers may have at least one layer overlapping the redistribution via, which is positioned not to overlap multiple UBM vias but to overlap an internal region closer to the center of the UBM layer.
- The semiconductor package includes a redistribution structure with multiple redistribution layers.
- A semiconductor chip is placed on one surface of the redistribution structure.
- The frame has a wiring structure connected to a redistribution via of the redistribution layer.
- UBM layers with UBM vias are present on the other surface of the redistribution structure.
- At least one UBM layer overlaps the redistribution via.
- The redistribution via does not overlap multiple UBM vias.
- The redistribution via overlaps an internal region closer to the center of the UBM layer.
Potential applications of this technology:
- Semiconductor packaging and assembly processes.
- Integrated circuit manufacturing.
Problems solved by this technology:
- Efficient redistribution of signals within a semiconductor package.
- Improved connectivity between the semiconductor chip and the frame.
Benefits of this technology:
- Enhanced performance and reliability of semiconductor packages.
- Increased signal integrity and reduced signal loss.
- Simplified manufacturing processes for semiconductor packages.
Original Abstract Submitted
A semiconductor package includes: a redistribution structure having a first surface and a second surface and including a plurality of redistribution layers, the plurality of redistribution layers including first and second redistribution layers adjacent to the first and second surfaces, respectively,; a semiconductor chip disposed on the first surface; a frame including a wiring structure connected to a first redistribution via of the first redistribution layer; and UBM layers disposed on the second surface and having a plurality of UBM vias. The UBM layers may include at least one UBM layer overlapping the first redistribution via, and the first redistribution via may be disposed so as not to overlap a plurality of UBM vias of the at least one UBM layer and to overlap an internal region closer to a central point of the at least one UBM layer than the plurality of UBM vias.
