18341490. SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
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SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME
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SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18341490 titled 'SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME
Simplified Explanation
The semiconductor package described in the patent application consists of multiple semiconductor chips stacked on top of each other with dielectric layers in between. The first semiconductor chip has connection terminals on one surface and a dielectric layer on the other surface. The second semiconductor chip is placed on top of the first dielectric layer and has a dielectric layer on one surface and another semiconductor chip on the opposite surface. An adhesive layer is used to bond the second and third semiconductor chips together. Notably, the dielectric layers do not contain any wirings.
- The semiconductor package includes multiple stacked semiconductor chips with dielectric layers in between.
- The dielectric layers do not have any wirings.
- Connection terminals are present on one surface of the first semiconductor chip.
- An adhesive layer is used to bond the second and third semiconductor chips together.
Potential applications of this technology:
- This semiconductor package can be used in various electronic devices such as smartphones, tablets, and computers.
- It can be beneficial in high-density integrated circuits where space is limited.
- The stacked configuration allows for increased functionality and performance in a compact form factor.
Problems solved by this technology:
- The stacked configuration helps in reducing the overall size of the semiconductor package.
- The absence of wirings in the dielectric layers simplifies the manufacturing process.
- The adhesive layer ensures secure bonding between the semiconductor chips.
Benefits of this technology:
- Improved space efficiency due to the stacked configuration.
- Enhanced performance and functionality in a compact form factor.
- Simplified manufacturing process without wirings in the dielectric layers.
Original Abstract Submitted
A semiconductor package and method of fabricating the same are provided. The semiconductor package includes a first semiconductor chip including first and second surfaces opposite to each other; connection terminals on the first surface of the first semiconductor chip; a first dielectric layer on the second surface of the first semiconductor chip; a second semiconductor chip on the first dielectric layer and including a third surface opposite to the second surface and a fourth surface opposite to the third surface; a second dielectric layer on the third surface of the second semiconductor chip and in contact with the first dielectric layer; a third semiconductor chip on the fourth surface of the second semiconductor chip; and a first adhesive layer between the second semiconductor chip and the third semiconductor chip, the first dielectric layer and the second dielectric layer including no wirings.
