18341406. WAFER DICING METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES BY USING THE WAFER DICING METHOD simplified abstract (Samsung Electronics Co., Ltd.)

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WAFER DICING METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES BY USING THE WAFER DICING METHOD

Organization Name

Samsung Electronics Co., Ltd.

Inventor(s)

Youngchul Kwon of Suwon-si (KR)

Deoksuk Jang of Suwon-Si (KR)

WAFER DICING METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES BY USING THE WAFER DICING METHOD - A simplified explanation of the abstract

This abstract first appeared for US patent application 18341406 titled 'WAFER DICING METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES BY USING THE WAFER DICING METHOD

Simplified Explanation

The wafer dicing method described in the abstract involves preparing a wafer with device forming regions and a scribe lane region, forming semiconductor devices in the device forming regions, creating inner cracks in the scribe lane region using a multiple pulse laser beam, and separating the semiconductor devices along the inner cracks.

  • Formation of inner cracks in the scribe lane region using a multiple pulse laser beam with decreasing peak powers.
  • Separation of semiconductor devices along the inner cracks created in the scribe lane region.

Potential Applications

The technology can be applied in semiconductor manufacturing processes for efficient wafer dicing and device separation.

Problems Solved

1. Efficient and precise separation of semiconductor devices from a wafer. 2. Minimization of damage to the devices during the dicing process.

Benefits

1. Improved yield and quality of semiconductor devices. 2. Cost-effective wafer dicing method. 3. Enhanced productivity in semiconductor manufacturing.

Potential Commercial Applications

Optimized Wafer Dicing Method for Semiconductor Manufacturing

Possible Prior Art

Prior art may include traditional wafer dicing methods using mechanical saws or lasers for device separation.

Unanswered Questions

How does the technology compare to traditional wafer dicing methods in terms of efficiency and cost-effectiveness?

The article does not provide a direct comparison between the new method and traditional techniques. Further research or testing may be needed to evaluate the advantages of this technology over existing methods.

Are there any limitations or challenges in implementing this technology on a large scale in semiconductor manufacturing facilities?

The abstract does not address potential limitations or challenges that may arise when scaling up the use of this technology in industrial settings. Additional studies or pilot projects could help identify and address any obstacles to widespread adoption.


Original Abstract Submitted

A wafer dicing method includes preparing a wafer that includes a plurality of device forming regions and a scribe lane region that separates the plurality of device forming regions, forming a plurality of semiconductor devices in the plurality of device forming regions of the wafer, respectively, forming a plurality of inner cracks in the scribe lane region of the wafer by repeatedly irradiating a multiple pulse laser beam that includes a plurality of sub-laser beams along the scribe lane region, wherein the plurality of sub-laser beams have decreasing peak powers, and separating the plurality of semiconductor devices from each other along the plurality of inner cracks.