18340291. USING RETIRED PAGES HISTORY FOR INSTRUCTION TRANSLATION LOOKASIDE BUFFER (TLB) PREFETCHING IN PROCESSOR-BASED DEVICES simplified abstract (QUALCOMM Incorporated)

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USING RETIRED PAGES HISTORY FOR INSTRUCTION TRANSLATION LOOKASIDE BUFFER (TLB) PREFETCHING IN PROCESSOR-BASED DEVICES

Organization Name

QUALCOMM Incorporated

Inventor(s)

Ajay Kumar Rathee of San Jose CA (US)

Conrado Blasco of San Mateo CA (US)

USING RETIRED PAGES HISTORY FOR INSTRUCTION TRANSLATION LOOKASIDE BUFFER (TLB) PREFETCHING IN PROCESSOR-BASED DEVICES - A simplified explanation of the abstract

This abstract first appeared for US patent application 18340291 titled 'USING RETIRED PAGES HISTORY FOR INSTRUCTION TRANSLATION LOOKASIDE BUFFER (TLB) PREFETCHING IN PROCESSOR-BASED DEVICES

Simplified Explanation

The abstract describes a patent application for a history-based instruction TLB prefetcher circuit in processor-based devices. The circuit is designed to prefetch instructions by using the retired pages history.

  • The processor-based device includes a history-based instruction TLB prefetcher (HTP) circuit.
  • The HTP circuit determines when the first instruction of a page has been retired.
  • It also determines the virtual address (VA) of the first page.
  • The HTP circuit compares the first page VA with the value of the last retired page VA indicator.
  • If the first page VA differs from the indicator value, the HTP circuit stores the first page VA as the new indicator value.

Potential applications of this technology:

  • Processor-based devices such as computers, smartphones, and tablets could benefit from improved instruction prefetching.
  • This technology could enhance the performance and efficiency of processors by reducing instruction fetch latency.

Problems solved by this technology:

  • Instruction fetch latency can be a bottleneck in processor performance.
  • By prefetching instructions based on retired pages history, the HTP circuit reduces the time needed to fetch instructions, improving overall processor efficiency.

Benefits of this technology:

  • Improved instruction prefetching leads to faster and more efficient processing.
  • Reduced instruction fetch latency enhances the performance of processor-based devices.
  • The HTP circuit optimizes instruction retrieval by utilizing retired pages history, resulting in better overall system performance.


Original Abstract Submitted

Using retired pages history for instruction translation lookaside buffer (TLB) prefetching in processor-based devices is disclosed herein. In some exemplary aspects, a processor-based device is provided. The processor-based device comprises a history-based instruction TLB prefetcher (HTP) circuit configured to determine that a first instruction of a first page has been retired. The HTP circuit is further configured to determine a first page virtual address (VA) of the first page. The HTP circuit is also configured to determine that the first page VA differs from a value of a last retired page VA indicator of the HTP circuit. The HTP circuit is additionally configured to, responsive to determining that the first page VA differs from the value of the last retired page VA indicator of the HTP circuit, store the first page VA as the value of the last retired page VA indicator.

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