18335452. BITONIC SORTING ACCELERATOR simplified abstract (Texas Instruments Incorporated)

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BITONIC SORTING ACCELERATOR

Organization Name

Texas Instruments Incorporated

Inventor(s)

Indu Prathapan of Bangalore (IN)

Puneet Sabbarwal of Bangalore (IN)

Pankaj Gupta of Bangalore (IN)

BITONIC SORTING ACCELERATOR - A simplified explanation of the abstract

This abstract first appeared for US patent application 18335452 titled 'BITONIC SORTING ACCELERATOR

Simplified Explanation

The abstract describes an accelerator for bitonic sorting, which is a sorting algorithm used in parallel computing systems. The accelerator includes multiple compare-exchange circuits and a FIFO buffer associated with each circuit.

  • The compare-exchange circuits perform comparisons and exchanges between values in the FIFO buffers.
  • In the first mode, the circuit stores a previous value from a previous circuit or memory to its FIFO buffer and passes a FIFO value to the next circuit or memory.
  • In the second mode, the circuit compares the previous value with the FIFO value, stores the greater value in its FIFO buffer, and passes the lesser value to the next circuit or memory.
  • In the third mode, the circuit compares the previous value with the FIFO value, stores the lesser value in its FIFO buffer, and passes the greater value to the next circuit or memory.

Potential applications of this technology:

  • Parallel computing systems that require efficient sorting algorithms.
  • High-performance computing applications that involve large datasets.

Problems solved by this technology:

  • Efficient sorting of data in parallel computing systems.
  • Reducing the complexity and latency of sorting algorithms.

Benefits of this technology:

  • Improved performance and efficiency in sorting large datasets.
  • Simplified implementation of bitonic sorting algorithms.
  • Reduced latency in parallel computing systems.


Original Abstract Submitted

An accelerator for bitonic sorting includes a plurality of compare-exchange circuits and a first-in, first-out (FIFO) buffer associated with each of the compare-exchange circuits. An output of each FIFO buffer is a FIFO value. The compare-exchange circuits are configured to, in a first mode, store a previous value from a previous compare-exchange circuit or a memory to its associated FIFO buffer and pass a FIFO value from its associated FIFO buffer to a subsequent compare-exchange circuit or the memory; in a second mode, compare the previous value to the FIFO value, store the greater value to its associated FIFO buffer, and pass the lesser value to the subsequent compare-exchange circuit or the memory; and in a third mode, compare the previous value to the FIFO value, store the lesser value to its associated FIFO buffer, and pass the greater value to the subsequent compare-exchange circuit or the memory.

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