18320513. SEMICONDUCTOR PACKAGE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18320513 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the abstract includes a complex structure involving multiple layers and components to enhance the performance and reliability of the semiconductor chip.
- First redistribution structure with a redistribution layer
- First semiconductor chip positioned on the redistribution structure
- Insulating layer adjacent to the sidewall of the semiconductor chip
- Connection structure extending through the insulating layer
- First molding layer covering the semiconductor chip
- Second molding layer on top of the insulating layer and first molding layer
- Potential Applications:**
- Advanced electronic devices - High-performance computing systems - Automotive electronics
- Problems Solved:**
- Improved electrical connections - Enhanced thermal management - Increased reliability and durability
- Benefits:**
- Higher performance capabilities - Better heat dissipation - Longer lifespan of semiconductor devices
- Potential Commercial Applications:**
- Semiconductor industry - Electronics manufacturing companies - Research and development organizations
- Possible Prior Art:**
There are existing semiconductor packaging technologies that involve similar concepts of redistribution layers, insulating layers, and molding layers to protect and enhance the functionality of semiconductor chips. However, the specific combination and arrangement of these elements as described in the patent application may be novel and innovative.
- Unanswered Questions:**
- 1. What specific materials are used in the first and second molding layers, and how do they contribute to the overall performance of the semiconductor package?**
- The abstract mentions that the second molding layer includes a material different from the first molding layer, but it does not provide details on the specific materials used or their properties.
- 2. How does the positioning of the top surface of the semiconductor chip relative to the insulating layer impact the overall design and functionality of the semiconductor package?**
- The abstract states that the top surface of the semiconductor chip is lower than the top surface of the insulating layer, but it does not explain the reasoning behind this design choice or the potential benefits it offers.
Original Abstract Submitted
A semiconductor package includes a first redistribution structure including a first redistribution layer, a first semiconductor chip on the first redistribution structure, an insulating layer adjacent a sidewall of the first semiconductor chip on the first redistribution structure and spaced apart from the first semiconductor chip in a horizontal direction, a connection structure extending through the insulating layer in a vertical direction and electrically connected to the first redistribution layer, a first molding layer on a sidewall and a top surface of the first semiconductor chip, and a second molding layer directly on each of a top surface of the insulating layer and a top surface of the first molding layer. The second molding layer includes a material different from a material of the first molding layer, and the top surface of the first semiconductor chip is lower than the top surface of the insulating layer.
