View source for 18320456. SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME simplified abstract (Samsung Electronics Co., Ltd.)

=SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME=


==Organization Name==

[[:Category:Samsung Electronics Co., Ltd.|Samsung Electronics Co., Ltd.]]


[[Category:Samsung Electronics Co., Ltd.]]

==Inventor(s)==

[[:Category:Ji-Yong Park of Suwon-si (KR)|Ji-Yong Park of Suwon-si (KR)]][[Category:Ji-Yong Park of Suwon-si (KR)]]

[[:Category:Jong Bo Shim of Suwon-si (KR)|Jong Bo Shim of Suwon-si (KR)]][[Category:Jong Bo Shim of Suwon-si (KR)]]

[[:Category:Dae Hun Lee of Suwon-si (KR)|Dae Hun Lee of Suwon-si (KR)]][[Category:Dae Hun Lee of Suwon-si (KR)]]

[[:Category:Choong Bin Yim of Suwon-si (KR)|Choong Bin Yim of Suwon-si (KR)]][[Category:Choong Bin Yim of Suwon-si (KR)]]

==SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A simplified explanation of the abstract==


This abstract first appeared for US patent application 18320456 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

==Simplified Explanation==

The semiconductor package described in the abstract includes a first package substrate with distinct regions, connection elements of varying heights, semiconductor chips, a second package, and a mold layer for protection and insulation.

* The first package substrate has two non-overlapping regions.
* A first connection element with a specific height is connected to a first semiconductor chip.
* A second connection element with a different height is present on the second region of the substrate.
* A third connection element, also with a specific height, is electrically connected to the second connection element.
* A second package, containing a second package substrate and a second semiconductor chip, is placed on the third connection element.
* A mold layer covers parts of the first semiconductor chip, the second connection element, and the first package substrate, while exposing certain upper surfaces and having its own height.

== Potential Applications ==
The technology described in this patent application could be applied in various semiconductor packaging industries, such as electronics manufacturing, telecommunications, and consumer electronics.

== Problems Solved ==
This technology addresses the need for efficient and reliable semiconductor packaging solutions that can accommodate different heights of connection elements and semiconductor chips within a single package.

== Benefits ==
The benefits of this technology include improved connectivity, enhanced protection for semiconductor components, and potentially more compact and versatile semiconductor packages.

== Potential Commercial Applications ==
"Advanced Semiconductor Packaging Technology for Height Variability in Connection Elements"

== Possible Prior Art ==
There is no known prior art for this specific semiconductor packaging technology.

== Unanswered Questions ==
1. How does the varying height of connection elements impact the overall performance and reliability of the semiconductor package?
2. Are there any specific design considerations or limitations when implementing this technology in mass production processes?


==Original Abstract Submitted==

A semiconductor package includes a first package substrate having a first region and a second region, which do not overlap each other, a first connection element having a first height on the first region, a first semiconductor chip having a second height connected to the first connection element, a second connection element having a third height on the second region, a third connection element having a fourth height on the second connection element and electrically connected to the second connection element, a second package on the third connection element, the second package including a second package substrate and a second semiconductor chip, and a first mold layer covering at least a portion of the first semiconductor chip, covering at least a portion of the second connection element, covering the first package substrate, exposing upper surfaces of the first semiconductor chip and the second connection element, and having a fifth height.



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