18315349. DESIGN FOR TESTABILITY FOR FAULT DETECTION IN CLOCK GATE CONTROL CIRCUITS simplified abstract (QUALCOMM Incorporated)
Contents
- 1 DESIGN FOR TESTABILITY FOR FAULT DETECTION IN CLOCK GATE CONTROL CIRCUITS
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 DESIGN FOR TESTABILITY FOR FAULT DETECTION IN CLOCK GATE CONTROL CIRCUITS - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
DESIGN FOR TESTABILITY FOR FAULT DETECTION IN CLOCK GATE CONTROL CIRCUITS
Organization Name
Inventor(s)
Paul Policke of Cedar Park TX (US)
Preston Mcwithey of Austin TX (US)
DESIGN FOR TESTABILITY FOR FAULT DETECTION IN CLOCK GATE CONTROL CIRCUITS - A simplified explanation of the abstract
This abstract first appeared for US patent application 18315349 titled 'DESIGN FOR TESTABILITY FOR FAULT DETECTION IN CLOCK GATE CONTROL CIRCUITS
Simplified Explanation
The abstract describes an integrated circuit (IC) with cascaded clock gating control (CGC) circuits, an observation flip-flop, an input register for fault testing, and test enable control registers.
- The IC includes a set of cascaded CGC circuits.
- The first CGC circuit has a clock input for receiving a clock signal.
- An observation flip-flop is included with its clock input connected to the last CGC circuit.
- An input register provides logic zeros to the CGC circuits for stuck-at-one fault testing.
- Test enable control registers provide logic ones to CGC circuits not undergoing fault testing.
Potential Applications
The technology described in this patent application could be applied in various digital systems where clock gating control is necessary for power optimization and fault testing.
Problems Solved
This technology helps in reducing power consumption by controlling clock signals and enables efficient fault testing in digital circuits.
Benefits
The integrated circuit with cascaded CGC circuits offers improved power efficiency, enhanced fault testing capabilities, and overall better performance in digital systems.
Potential Commercial Applications
- "Power Optimization and Fault Testing in Digital Systems: Applications of Integrated Circuits with Cascaded CGC Circuits"
Possible Prior Art
There may be prior art related to clock gating control circuits, fault testing mechanisms, and integrated circuits with similar functionalities.
Unanswered Questions
How does this technology compare to existing clock gating control mechanisms in terms of power efficiency and fault testing capabilities?
The article does not provide a direct comparison with existing technologies in terms of power efficiency and fault testing capabilities.
Are there any specific industries or sectors where this technology is expected to have a significant impact?
The article does not mention any specific industries or sectors where the technology is expected to have a significant impact.
Original Abstract Submitted
An integrated circuit (IC), including: a set of cascaded clock gating control (CGC) circuits, wherein a first one of the set of cascaded CGC circuits includes a clock input configured to receive a clock signal; an observation flip-flop including a clock input coupled to a clock output of a last one of the set of cascaded CGC circuits; an input register configured to provide logic zeros (0s) to clock enable (CE) inputs of the set of cascaded CGC circuits pursuant to a stuck-at-one (SA1) fault testing on the CE input of a selected one of the set of cascaded CGC circuits; and a set of one or more test enable (TE) control registers configured to provide one or more logic ones (1s) to one or more TE inputs of one or more of the set of cascaded CGC circuits not undergoing the stuck-at-one (SA1) fault testing, respectively.
