18312331. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
- 1 SEMICONDUCTOR PACKAGE
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 How does this technology impact the overall cost of semiconductor packaging?
- 1.11 What are the environmental considerations of using this packaging method?
- 1.12 Original Abstract Submitted
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Kyung Don Mun of Suwon-si (KR)
Sang Cheon Park of Suwon-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18312331 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the abstract includes a buffer die, semiconductor chip stacks, and a mold layer covering the buffer die and side surfaces of the semiconductor chip stacks. Each semiconductor chip stack consists of multiple first semiconductor chips and a second semiconductor chip, with wiring parts, upper and lower connection structures, and a redistribution layer on the second semiconductor chip.
- Buffer die with semiconductor chip stacks:
- The package includes a buffer die that serves as a base for stacking semiconductor chips. - Multiple semiconductor chip stacks are placed on the buffer die, forming a compact structure.
- Wiring parts and connection structures:
- Each semiconductor chip in the package contains wiring parts with multilayer wirings for electrical connections. - Upper and lower connection structures on each chip provide conductive pads for inter-chip communication.
- Redistribution layer on the second semiconductor chip:
- The second semiconductor chip in each stack features a redistribution layer with insulating and redistribution pads for enhanced connectivity.
Potential Applications
The technology described in the patent application can be applied in various electronic devices requiring compact and efficient semiconductor packaging, such as mobile phones, tablets, and IoT devices.
Problems Solved
This technology solves the problem of optimizing space utilization in semiconductor packaging while ensuring reliable electrical connections between stacked chips.
Benefits
The benefits of this technology include increased packaging density, improved electrical performance, and enhanced reliability in semiconductor devices.
Potential Commercial Applications
The semiconductor package design outlined in the patent application has potential commercial applications in the semiconductor manufacturing industry, particularly in the production of high-density and high-performance electronic devices.
Possible Prior Art
One possible prior art for this technology could be the development of 3D stacked integrated circuits with advanced packaging techniques to improve performance and efficiency in electronic devices.
Unanswered Questions
How does this technology impact the overall cost of semiconductor packaging?
The article does not address the potential cost implications of implementing this semiconductor packaging technology.
What are the environmental considerations of using this packaging method?
The environmental impact of the materials and processes involved in this semiconductor packaging method is not discussed in the article.
Original Abstract Submitted
A semiconductor package includes a buffer die, semiconductor chip stacks stacked on the buffer die, each of the semiconductor chip stacks including a plurality of first semiconductor chips and a second semiconductor chip on the plurality of first semiconductor chips, and a mold layer covering an upper surface of the buffer die and side surfaces of the semiconductor chip stacks. Each of the first semiconductor chips and the second semiconductor chip includes a wiring part including multilayer wirings, an upper connection structure on the wiring part and having a plurality of upper conductive pads and a lower connection structure under the wiring part and having a plurality of lower conductive pads, and the second semiconductor chip further includes a redistribution layer on the upper connection structure and having an insulating layer and a plurality of redistribution pads in the insulating layer.
