18309250. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Choong Bin Yim of Suwon-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18309250 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the patent application includes a memory semiconductor package, an adhesive layer, a wire, a logic semiconductor chip, a first connection terminal, and a molding layer. The memory semiconductor package is on a first surface of a first substrate, with the adhesive layer between them. The wire extends from the memory semiconductor package to the first substrate, where it is connected. The logic semiconductor chip is also on the first surface of the first substrate, with a first connection terminal between them. The molding layer covers the components, with the memory semiconductor package having a smaller height than the logic semiconductor chip, and the uppermost surface of the molding layer and the logic semiconductor chip being coplanar.
- Memory semiconductor package on first surface of first substrate
- Adhesive layer between memory semiconductor package and first substrate
- Wire connecting memory semiconductor package to first substrate
- Logic semiconductor chip on first surface of first substrate
- First connection terminal between logic semiconductor chip and first substrate
- Molding layer covering components, with memory semiconductor package having smaller height than logic semiconductor chip
Potential Applications
- Semiconductor packaging industry - Electronics manufacturing
Problems Solved
- Efficient integration of memory and logic semiconductor components - Improved packaging design for semiconductor devices
Benefits
- Compact design - Enhanced performance - Cost-effective manufacturing process
Original Abstract Submitted
A semiconductor package includes a first substrate, a memory semiconductor package on a first surface of the first substrate, an adhesive layer between the first surface of the first substrate and the memory semiconductor package, a wire extending from an upper surface of the memory semiconductor package and connected to the first substrate, a logic semiconductor chip on the first surface of the first substrate, a first connection terminal between the first surface of the first substrate and the logic semiconductor chip, and a molding layer, wherein a first height of the memory semiconductor package is smaller than a second height of the logic semiconductor chip, and wherein an uppermost surface of the molding layer and the upper surface of the logic semiconductor chip are coplanar.
