18242884. PERFORMING SELECT GATE INTEGRITY CHECKS TO IDENTIFY AND INVALIDATE DEFECTIVE BLOCKS simplified abstract (MICRON TECHNOLOGY, INC.)
PERFORMING SELECT GATE INTEGRITY CHECKS TO IDENTIFY AND INVALIDATE DEFECTIVE BLOCKS
Organization Name
Inventor(s)
Zhongguang Xu of San Jose CA (US)
Zhenlei Shen of Milpitas CA (US)
Murong Lang of San Jose CA (US)
PERFORMING SELECT GATE INTEGRITY CHECKS TO IDENTIFY AND INVALIDATE DEFECTIVE BLOCKS - A simplified explanation of the abstract
This abstract first appeared for US patent application 18242884 titled 'PERFORMING SELECT GATE INTEGRITY CHECKS TO IDENTIFY AND INVALIDATE DEFECTIVE BLOCKS
Simplified Explanation
The patent application describes a system and method involving a memory device and a processing device. The processing device receives an enhanced erase command from a host system, which references a specific block. It then performs a lookup to determine if the block is marked in a grown bad block (GBB) data structure. The GBB data structure is used to track blocks that have a defective select gate. If the processing device determines that the block is marked in the GBB data structure, it discards the enhanced erase command.
- The system includes a memory device and a processing device.
- The processing device receives an enhanced erase command from a host system.
- The enhanced erase command references a specific block.
- The processing device performs a lookup to check if the block is marked in a grown bad block (GBB) data structure.
- The GBB data structure tracks blocks with a defective select gate.
- If the block is marked in the GBB data structure, the processing device discards the enhanced erase command.
Potential applications of this technology:
- Memory devices with enhanced erase commands.
- Systems that track and manage defective blocks in memory devices.
Problems solved by this technology:
- Efficiently managing defective blocks in memory devices.
- Avoiding the use of enhanced erase commands on blocks with defective select gates.
Benefits of this technology:
- Improved memory device performance.
- Enhanced reliability by avoiding the use of defective blocks.
- Efficient use of resources by discarding unnecessary erase commands.
Original Abstract Submitted
Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising receiving, from a host system, an enhanced erase command referencing a block; performing a lookup to determine whether the block is marked in a grown bad block (GBB) data structure used to track blocks that have a defective select gate; and responsive to determining that the block is marked in the GBB data structure, discarding the enhanced erase command.
