18231762. APPARATUS AND METHOD FOR MAPPING FOUNDATIONAL COMPONENTS DURING DESIGN PORTING FROM ONE PROCESS TECHNOLOGY TO ANOTHER PROCESS TECHNOLOGY simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)

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APPARATUS AND METHOD FOR MAPPING FOUNDATIONAL COMPONENTS DURING DESIGN PORTING FROM ONE PROCESS TECHNOLOGY TO ANOTHER PROCESS TECHNOLOGY

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Chih-yuan Stephen Yu of San Jose CA (US)

Boh-Yi Huang of San Jose CA (US)

Chao-Chun Lo of San Jose CA (US)

Xiang Guo of San Jose CA (US)

APPARATUS AND METHOD FOR MAPPING FOUNDATIONAL COMPONENTS DURING DESIGN PORTING FROM ONE PROCESS TECHNOLOGY TO ANOTHER PROCESS TECHNOLOGY - A simplified explanation of the abstract

This abstract first appeared for US patent application 18231762 titled 'APPARATUS AND METHOD FOR MAPPING FOUNDATIONAL COMPONENTS DURING DESIGN PORTING FROM ONE PROCESS TECHNOLOGY TO ANOTHER PROCESS TECHNOLOGY

Simplified Explanation

The abstract describes a method and system for migrating an existing ASIC (Application-Specific Integrated Circuit) design from one semiconductor fabrication process to another. The method involves parsing the gate-level netlist of the existing ASIC design and converting it into standard cells. Mapping tables are then created to map the parsed standard cells into equivalent target standard cells implemented in the second semiconductor fabrication process. The parsed standard cells are mapped into the equivalent target standard cells using the mapping tables, and a target gate-level netlist describing the ASIC design in terms of the equivalent target standard cells is generated.

  • The method involves parsing the gate-level netlist of an existing ASIC design.
  • The parsed netlist is converted into standard cells.
  • Mapping tables are created to map the parsed standard cells into equivalent target standard cells.
  • The parsed standard cells are mapped into the equivalent target standard cells using the mapping tables.
  • A target gate-level netlist describing the ASIC design in terms of the equivalent target standard cells is generated.

Potential applications of this technology:

  • Semiconductor companies can use this method to migrate their existing ASIC designs to a new semiconductor fabrication process without having to redesign the entire circuit.
  • The method allows for easier integration of new semiconductor technologies into existing ASIC designs.

Problems solved by this technology:

  • Migration of ASIC designs from one semiconductor fabrication process to another can be a complex and time-consuming process. This method provides a systematic approach to simplify the migration process.
  • Redesigning an entire ASIC circuit for a new semiconductor fabrication process can be costly. This method allows for the reuse of existing ASIC designs, reducing costs and development time.

Benefits of this technology:

  • Cost savings: The method allows for the reuse of existing ASIC designs, reducing the need for complete redesigns and saving costs.
  • Time savings: The systematic approach of the method simplifies the migration process, saving time and effort.
  • Flexibility: Semiconductor companies can easily migrate their ASIC designs to new semiconductor fabrication processes, allowing for the integration of new technologies and improvements.


Original Abstract Submitted

A method and system for migrating an existing ASIC design from one semiconductor fabrication process to another are disclosed herein. In some embodiments, a method for migrating the existing ASIC design comprises parsing the gate-level netlist one row at a time into one or more standard cells forming the ASIC design, forming a plurality of mapping tables having mapping rules for mapping the parsed one or more standard cells into equivalent target standard cells implemented in the second semiconductor fabrication process, mapping the parsed one or more standard cells into the equivalent target standard cells using the plurality of mapping tables, and generating a target gate-level netlist describing the ASIC design in terms of the equivalent target standard cells.

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