18229039. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18229039 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the patent application includes multiple semiconductor chips stacked on top of each other with redistribution structures in between. Here are the key points of the innovation:
- The package consists of a first semiconductor package with a first semiconductor chip and a second semiconductor chip stacked on top of each other.
- The first semiconductor chip has a device layer and a semiconductor substrate with a through electrode.
- The second semiconductor chip is placed on top of the first semiconductor chip and has its own device layer and semiconductor substrate.
- A molding member surrounds the first semiconductor chip to provide protection.
- A second redistribution structure is located on the upper surface of the molding member.
- A second semiconductor package is placed on the second redistribution structure, with a third semiconductor chip inside.
Potential applications of this technology:
- Advanced semiconductor packaging for compact electronic devices.
- High-density integrated circuits for improved performance.
- Multi-chip modules for data processing applications.
Problems solved by this technology:
- Efficient stacking of multiple semiconductor chips in a compact space.
- Enhanced thermal management for better performance.
- Protection of delicate semiconductor components.
Benefits of this technology:
- Increased functionality in a smaller form factor.
- Improved reliability and durability of semiconductor packages.
- Enhanced performance of electronic devices.
Original Abstract Submitted
A semiconductor package includes a first redistribution structure, a first semiconductor package on the first redistribution structure, the first semiconductor package including a first semiconductor chip which includes a first device layer and a first semiconductor substrate including a through electrode, a second semiconductor chip which is on the first semiconductor chip and includes a second device layer and a second semiconductor substrate, and a molding member surrounding the first semiconductor chip, a second redistribution structure on an upper surface of the molding member, and a second semiconductor package on the second redistribution structure, the second semiconductor package including a third semiconductor chip, wherein the second semiconductor chip is apart from the second semiconductor package in a horizontal direction, and an upper surface of the second semiconductor chip is higher than the upper surface of the molding member.
