18218885. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

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SEMICONDUCTOR PACKAGE

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Byungho Kim of Suwon-si (KR)

Youngchan Ko of Suwon-si (KR)

Gyeongho Kim of Suwon-si (KR)

Yongkoon Lee of Suwon-si (KR)

Myungdo Cho of Suwon-si (KR)

Sangseok Hong of Suwon-si (KR)

SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18218885 titled 'SEMICONDUCTOR PACKAGE

Simplified Explanation

The abstract describes a fan-out semiconductor package with various structures and layers for redistribution and wiring.

  • The package includes a wiring substrate with first fan-in, fan-out, and second fan-in regions.
  • It also includes first and second fan-in chip structures, first redistribution elements on the bottom surface, and a second redistribution structure on the top surface.
  • The second redistribution structure extends to the first fan-in and fan-out regions, with second redistribution vias and a seed layer.

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      1. Potential Applications
  • Semiconductor packaging for electronic devices
  • Integrated circuits in consumer electronics
  • High-performance computing systems
      1. Problems Solved
  • Efficient redistribution of signals in a semiconductor package
  • Improved connectivity between different chip structures
  • Enhanced performance and reliability of electronic devices
      1. Benefits
  • Higher integration density
  • Improved signal transmission
  • Enhanced thermal performance
  • Increased reliability and durability of electronic devices


Original Abstract Submitted

A fan-out semiconductor package includes a wiring substrate including a first fan-in region, a fan-out region surrounding the first fan-in region, and a second fan-in region, a first fan-in chip structure, a second fan-in chip structure, a first redistribution structure including first redistribution elements disposed on a bottom surface of the wiring substrate, and a second redistribution structure disposed on a top surface of the wiring substrate, and a chip wiring structure formed on a top surface of the second chip, and the second redistribution structure includes a second redistribution layer extending to the first fan-in region and the fan-out region, a plurality of second redistribution vias integrally formed with the second redistribution layer and extending downward, and a seed layer surrounding the second redistribution layer and bottom surfaces of the plurality of second redistribution vias.