View source for 18216186. ARITHMETIC PROCESSING DEVICE AND ARITHMETIC PROCESSING METHOD simplified abstract (Fujitsu Limited)

=ARITHMETIC PROCESSING DEVICE AND ARITHMETIC PROCESSING METHOD=


==Organization Name==

[[:Category:Fujitsu Limited|Fujitsu Limited]]


[[Category:Fujitsu Limited]]

==Inventor(s)==

[[:Category:Ryohei Okazaki of Kawasaki (JP)|Ryohei Okazaki of Kawasaki (JP)]][[Category:Ryohei Okazaki of Kawasaki (JP)]]

==ARITHMETIC PROCESSING DEVICE AND ARITHMETIC PROCESSING METHOD - A simplified explanation of the abstract==


This abstract first appeared for US patent application 18216186 titled 'ARITHMETIC PROCESSING DEVICE AND ARITHMETIC PROCESSING METHOD

==Simplified Explanation==

The patent application describes a branch predictor in an arithmetic processing device that includes a prediction holder for managing branch prediction values for conditional branch instructions. The branch instruction issuance scheduler is responsible for handling branch prediction misses and issuing refetch requests and repair requests to the branch predictor.

* The branch predictor in the arithmetic processing device manages branch prediction values for conditional branch instructions.
* The branch instruction issuance scheduler handles branch prediction misses by issuing refetch requests and repair requests to the branch predictor.

== Potential Applications ==
This technology could be applied in various computing devices that require efficient branch prediction mechanisms, such as processors, microcontrollers, and other hardware systems.

== Problems Solved ==
1. Efficient management of branch prediction values for conditional branch instructions.
2. Handling branch prediction misses effectively to improve processing performance.

== Benefits ==
1. Improved processing efficiency by optimizing branch prediction mechanisms.
2. Enhanced overall performance of arithmetic processing devices.
3. Reduction in processing delays due to branch prediction misses.

== Potential Commercial Applications ==
Optimizing branch prediction mechanisms in processors for faster and more efficient computing performance.

== Possible Prior Art ==
Prior art in branch prediction mechanisms in processors and computing devices may include various techniques such as static prediction, dynamic prediction, and hybrid prediction models.

== Unanswered Questions ==

=== How does the branch predictor handle conflicting predictions for conditional branch instructions? ===
The patent application does not provide specific details on how the branch predictor resolves conflicting predictions for conditional branch instructions.

=== What impact does the branch prediction mechanism have on overall processing speed and efficiency? ===
The patent application does not elaborate on the potential impact of the branch prediction mechanism on the overall processing speed and efficiency of the arithmetic processing device.


==Original Abstract Submitted==

An arithmetic processing device executes instructions by pipeline processing. In the arithmetic processing device, a branch predictor includes a prediction holder holding a prediction value of a consecutively taken branch count, a current taken branch count, and a prediction value of a remaining taken branch count for conditional branch instructions. A branch instruction issuance scheduler outputs an instruction refetch request upon a branch prediction miss of a conditional branch instruction held at an entry other than a head of a branch instruction completion queue holding branch instructions to be completed, and a repair request to the branch predictor for conditional branch instructions held between the entry and the head of the queue. In response to the requests, the branch predictor updates the prediction value of the remaining taken branch count for the conditional branch instructions corresponding to the repair request.



[[Category:G06F9/38]]