18213386. SEMICONDUCTOR PACKAGE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
- 1 SEMICONDUCTOR PACKAGE
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 How does this technology impact the overall performance of semiconductor packages?
- 1.11 What are the potential limitations or challenges associated with implementing this technology?
- 1.12 Original Abstract Submitted
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
SEUNGDUK Baek of Suwon-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18213386 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the abstract includes two semiconductor chips bonded together, allowing their test patterns to face each other. The first semiconductor chip has a first test pattern with connection pads and an out-pad, while the second semiconductor chip has a second test pattern with connection pads, an in-pad, and an out-pad. The connection pads of the first and second test patterns are connected in series to form a series wiring pattern.
- First semiconductor chip with a first test pattern
- Second semiconductor chip with a second test pattern
- Connection pads and out-pad on the first test pattern
- Connection pads, in-pad, and out-pad on the second test pattern
- Series wiring pattern formed by connecting the connection pads in series
Potential Applications
The technology described in this patent application could be applied in the semiconductor industry for improving the testing and connectivity of semiconductor chips in packages.
Problems Solved
This technology solves the problem of efficiently connecting and testing multiple semiconductor chips within a single package.
Benefits
The benefits of this technology include improved testing efficiency, enhanced connectivity, and potentially reduced manufacturing costs.
Potential Commercial Applications
- Semiconductor packaging industry advancements
Possible Prior Art
There may be prior art related to semiconductor chip packaging and testing methods, but specific examples are not provided in this abstract.
Unanswered Questions
How does this technology impact the overall performance of semiconductor packages?
The abstract does not provide information on how this technology may impact the overall performance of semiconductor packages.
What are the potential limitations or challenges associated with implementing this technology?
The abstract does not address any potential limitations or challenges that may arise from implementing this technology.
Original Abstract Submitted
A semiconductor package includes a first semiconductor chip on a substrate and including a first semiconductor substrate and a first test pattern on a first surface of the first semiconductor substrate, and a second semiconductor chip on the first semiconductor chip and including a second semiconductor substrate and a second test pattern on a second surface of the second semiconductor substrate. The first and second semiconductor chips bonded to allow the first test pattern to face the second test pattern. The first test pattern includes a first in-pad, first connection pads, and a first out-pad. The second test pattern includes a second in-pad bonded to the first in-pad, a second out-pad bonded to the first out-pad, and second connection pads bonded to the first connection pads. The first and second connection pads are connected in series to alternately connect with each other and form a series wiring pattern, so that each first connection pad connects to another first connection pad in one direction along the series wiring pattern and to a second connection pad in an opposite direction along the series wiring pattern.
