18209286. SEMICONDUCTOR PACKAGE AND PACKAGE-ON-PACKAGE HAVING THE SAME simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR PACKAGE AND PACKAGE-ON-PACKAGE HAVING THE SAME
Organization Name
Inventor(s)
SEMICONDUCTOR PACKAGE AND PACKAGE-ON-PACKAGE HAVING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18209286 titled 'SEMICONDUCTOR PACKAGE AND PACKAGE-ON-PACKAGE HAVING THE SAME
Simplified Explanation
The semiconductor package described in the patent application includes a redistribution layer with conductive lines, conductive vias, and lower pads, a semiconductor chip, external connection terminals, and electrical paths for testing the conductive lines and vias.
- The semiconductor package has a redistribution layer with conductive lines, conductive vias, and lower pads.
- A semiconductor chip is mounted on the redistribution layer.
- External connection terminals are attached to the lower pads for external connections.
- Electrical paths are included in the package for testing the conductive lines and vias.
- Potential Applications
- Semiconductor packaging industry
- Electronics manufacturing
- Problems Solved
- Testing of conductive lines and vias in a semiconductor package
- Efficient redistribution of electrical connections in a package
- Benefits
- Improved testing capabilities for semiconductor packages
- Enhanced reliability of electrical connections
- Simplified manufacturing processes for semiconductor devices
Original Abstract Submitted
A semiconductor package includes: a redistribution layer including a plurality of conductive lines; a plurality of conductive vias each connected to at least one of the plurality of conductive lines; and a plurality of lower pads each connected to one of the plurality of conductive vias; a semiconductor chip on the redistribution layer; and a plurality of external connection terminals attached to the plurality of lower pads; and a plurality of electrical paths, wherein each of the plurality of electrical paths includes at least one of the plurality of conductive lines and at least one of the plurality of conductive vias. The plurality of electrical paths is configured for testing the plurality of conductive lines and the plurality of conductive vias and is connected to at least four of the external connection test terminals.
