18203223. OUT-OF-ORDER PROGRAMMING OF FIRST WORDLINE IN A PHYSICAL UNIT OF A MEMORY DEVICE simplified abstract (MICRON TECHNOLOGY, INC.)

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OUT-OF-ORDER PROGRAMMING OF FIRST WORDLINE IN A PHYSICAL UNIT OF A MEMORY DEVICE

Organization Name

MICRON TECHNOLOGY, INC.

Inventor(s)

Deping He of Boise ID (US)

Ching-Huang Lu of Fremont CA (US)

OUT-OF-ORDER PROGRAMMING OF FIRST WORDLINE IN A PHYSICAL UNIT OF A MEMORY DEVICE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18203223 titled 'OUT-OF-ORDER PROGRAMMING OF FIRST WORDLINE IN A PHYSICAL UNIT OF A MEMORY DEVICE

Simplified Explanation

The memory device described in the patent application includes a memory array with memory cells and control logic.

  • The control logic performs operations such as programming memory cells in a sequential manner.
  • The programming starts at a second wordline and proceeds through sequentially-ordered wordlines of a physical unit.
  • The first wordline is associated with memory cells adjacent to select gate (SG) transistors.
  • The wordlines are numbered based on their distance from the SG transistors.
  • After programming the memory cells associated with the second wordline or completing programming the physical unit, the memory cells associated with the first wordline are programmed.

Potential applications of this technology:

  • Memory devices used in various electronic devices such as smartphones, computers, and servers.
  • Solid-state drives (SSDs) and other storage devices that require efficient memory programming.

Problems solved by this technology:

  • Efficient programming of memory cells in a memory array.
  • Sequential programming of memory cells in a physical unit, improving overall memory device performance.

Benefits of this technology:

  • Improved memory programming efficiency and performance.
  • Enhanced reliability and endurance of memory devices.
  • Enables faster data access and storage operations.


Original Abstract Submitted

A memory device includes a memory array comprising memory cells associated with a plurality of wordlines control logic that is to perform operations including: causing memory cells of a physical unit of the memory array to be programmed starting at a second wordline, which is adjacent to a first wordline of the memory array, and proceeding sequentially through a plurality of sequentially-ordered wordlines of the physical unit, wherein the first wordline is associated with memory cells that are adjacent to one or more select gate (SG) transistors of the memory array, and the sequentially-ordered wordlines are numbered according to a distance away from the one or more SG transistors; and at least one of after the memory cells associated with the second wordline are programmed or after completion of programming the physical unit, causing the memory cells associated with the first wordline to be programmed.

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