18202375. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Joonghyun Baek of Suwon-si (KR)
Hyunsoo Chung of Suwon-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18202375 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the patent application includes a base chip, semiconductor chips with front pads and rear pads, bumps between the chips, a dam structure on the rear pads, and insulating adhesive layers around the bumps and dam structure. The rear pads have first pads in the center region connected to through-vias and second pads in the peripheral region, including a line pad with a polygonal shape.
- Base chip with semiconductor chips and through-vias
- Front and rear pads on semiconductor chips
- Bumps between chips
- Dam structure on rear pads
- Insulating adhesive layers surrounding bumps and dam structure
- Rear pads with first pads in center region and second pads in peripheral region, including a polygonal line pad
- Dam structure with a bent shape
Potential Applications
- Advanced semiconductor packaging technology
- Improved electrical connections in semiconductor devices
- Enhanced thermal management in electronic components
Problems Solved
- Ensuring reliable electrical connections between semiconductor chips
- Managing heat dissipation effectively in compact electronic devices
- Enhancing overall performance and reliability of semiconductor packages
Benefits
- Increased functionality and efficiency of semiconductor devices
- Improved durability and longevity of electronic components
- Enhanced performance in high-demand applications
Original Abstract Submitted
A semiconductor package includes: a base chip; semiconductor chips disposed on the base chip and including front pads disposed on a front surface opposing the base chip, rear pads disposed on a rear surface opposing the front surface, and through-vias; bumps disposed between the semiconductor chips; a dam structure disposed on at least a portion of the rear pads; and insulating adhesive layers at least partially surrounding the bumps and the dam structure, wherein the rear pads include first pads that are disposed in a center region that crosses a center of the rear surface and that are electrically connected to the through-vias, and second pads that are disposed in a peripheral region adjacent to the center region, wherein the second pads include a line pad of which at least a portion has a polygonal shape, and wherein the dam structure has a bent shape.
