18197258. MEMORY DEVICE INCLUDING PAGE BUFFER CIRCUIT simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
MEMORY DEVICE INCLUDING PAGE BUFFER CIRCUIT
Organization Name
Inventor(s)
MEMORY DEVICE INCLUDING PAGE BUFFER CIRCUIT - A simplified explanation of the abstract
This abstract first appeared for US patent application 18197258 titled 'MEMORY DEVICE INCLUDING PAGE BUFFER CIRCUIT
Simplified Explanation
The memory device described in the patent application includes a memory cell array with multiple memory cells, and a page buffer circuit with multiple page buffer units connected to the memory cells via bit lines, as well as cache latches corresponding to the page buffer units. Each page buffer unit has a pass transistor connected to a sensing node and controlled by a pass control signal. During data sensing, a selected page buffer unit's sensing node is connected to an unselected page buffer unit's sensing node.
- Memory device with memory cell array and page buffer circuit
- Page buffer units connected to memory cells via bit lines
- Cache latches corresponding to page buffer units
- Pass transistors in page buffer units controlled by pass control signal
- Active connection between selected and unselected page buffer units during data sensing
Potential Applications
- Solid-state drives
- Embedded systems
- Mobile devices
Problems Solved
- Efficient data sensing in memory devices
- Reduced power consumption
- Improved performance in memory operations
Benefits
- Faster data sensing
- Lower power consumption
- Enhanced memory device performance
Original Abstract Submitted
A memory device includes a memory cell array including a plurality of memory cells, and a page buffer circuit including a plurality of page buffer units respectively connected to the plurality of memory cells via a plurality of bit lines, and a plurality of cache latches respectively corresponding to the plurality of page buffer units. Each of the plurality of page buffer units includes a pass transistor that is connected to a corresponding sensing node and is driven according to a pass control signal, and the memory device is configured such that in a data sensing period, a sensing node of a selected page buffer unit among the plurality of page buffer units is actively connected to a sensing node of an unselected page buffer unit among the plurality of page buffer units.
