18188157. POWER MANAGEMENT CHIP, ELECTRONIC DEVICE HAVING THE SAME, AND OPERATING METHOD THEREOF simplified abstract (Samsung Electronics Co., Ltd.)

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POWER MANAGEMENT CHIP, ELECTRONIC DEVICE HAVING THE SAME, AND OPERATING METHOD THEREOF

Organization Name

Samsung Electronics Co., Ltd.

Inventor(s)

Huidong Gwon of SUWON-SI (KR)

Taehwang Kong of SUWON-SI (KR)

Minjae Kim of SUWON-SI (KR)

Junhyeok Yang of SUWON-SI (KR)

Yunho Lee of SUWON-SI (KR)

POWER MANAGEMENT CHIP, ELECTRONIC DEVICE HAVING THE SAME, AND OPERATING METHOD THEREOF - A simplified explanation of the abstract

This abstract first appeared for US patent application 18188157 titled 'POWER MANAGEMENT CHIP, ELECTRONIC DEVICE HAVING THE SAME, AND OPERATING METHOD THEREOF

Simplified Explanation

The patent application describes a power management chip with various components for efficient power control and management.

  • Gate driver outputs signals to drive power switches.
  • Multiplexer receives error detect and gate signals to control power switch based on mode select signal.
  • Inductor detection logic detects external inductor and outputs mode select signal accordingly.
  • Comparator compares internal and feedback node voltages based on detection signal.

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      1. Potential Applications
  • Power management in electronic devices.
  • Battery charging systems.
  • Power supply units.
      1. Problems Solved
  • Efficient power control.
  • Detection of external inductors.
  • Voltage comparison for accurate power management.
      1. Benefits
  • Improved power efficiency.
  • Enhanced control over power switches.
  • Detection of external components for optimized performance.


Original Abstract Submitted

A power management chip includes a gate driver configured to output a first gate signal driving a first power switch and a second gate signal driving the second power switch, a multiplexer configured to receive an error detect signal from a first error amplifier and a first gate signal from the gate driver, and drive the first power switch with either of the error detect signal or the first gate signal in response to a mode select signal; an inductor detection logic configured to receive the inductor detect signal, output a comparison detect signal and a pulse signal for detecting an external inductor, and output the mode select signal corresponding to a result of the detecting, and a comparator comparing an internal output voltage of an output node and an output voltage of the feedback node in response to the comparison detect signal.