18177877. MEMORY SYSTEM AND METHOD FOR CONTROLLING SEMICONDUCTOR MEMORY simplified abstract (Kioxia Corporation)
Contents
MEMORY SYSTEM AND METHOD FOR CONTROLLING SEMICONDUCTOR MEMORY
Organization Name
Inventor(s)
Kiwamu Watanabe of Kawasaki Kanagawa (JP)
Yuko Noda of Kawasaki Kanagawa (JP)
Tsukasa Tokutomi of Kamakura Kanagawa (JP)
Yoshiki Takai of Fujisawa Kanagawa (JP)
MEMORY SYSTEM AND METHOD FOR CONTROLLING SEMICONDUCTOR MEMORY - A simplified explanation of the abstract
This abstract first appeared for US patent application 18177877 titled 'MEMORY SYSTEM AND METHOD FOR CONTROLLING SEMICONDUCTOR MEMORY
Simplified Explanation
The abstract describes a memory controller that receives data through different reads with varying voltages. The controller instructs the memory to perform additional reads based on the differences between the data values and an expected value.
- The memory controller receives data through multiple reads with different voltages.
- The controller compares the differences between the data values and an expected value.
- Based on the comparison, the memory controller instructs the memory to perform additional reads with different voltages.
Potential Applications:
- This technology can be applied in various memory systems, such as computer RAM or storage devices.
- It can improve the efficiency and accuracy of data retrieval and storage processes.
Problems Solved:
- The technology addresses the issue of data inconsistency or errors in memory systems.
- It helps optimize the reading process by adjusting voltages based on data differences.
Benefits:
- Improved data accuracy and consistency in memory systems.
- Enhanced efficiency in data retrieval and storage operations.
- Potential for faster and more reliable memory performance.
Original Abstract Submitted
A memory controller receives first, second, and third data by first, second, and third reads, specifying a first address, and respectively specifying first, second, and third read voltages higher in this order. The controller instructs a memory to execute a fourth read specifying a fourth read voltage lower than the first read voltage and the first address when a first difference between a first-value-bit count of the first data and an expected value is smaller than a second difference between a first-value-bit count of the third data and the expected value. The memory controller instructs the memory to execute a fifth read specifying a fifth read voltage higher than the third read voltage and the first address when the first difference is larger than the second difference.
