18176268. CONTROLLING MEMORY MODULE CLOCK BUFFER POWER IN A SYSTEM WITH A SINGLE MEMORY CLOCK PER MEMORY MODULE simplified abstract (Dell Products L.P.)

CONTROLLING MEMORY MODULE CLOCK BUFFER POWER IN A SYSTEM WITH A SINGLE MEMORY CLOCK PER MEMORY MODULE

Organization Name

Dell Products L.P.

Inventor(s)

Isaac Q. Wang of Austin TX (US)

Lee B. Zaretsky of Nazare (PT)

CONTROLLING MEMORY MODULE CLOCK BUFFER POWER IN A SYSTEM WITH A SINGLE MEMORY CLOCK PER MEMORY MODULE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18176268 titled 'CONTROLLING MEMORY MODULE CLOCK BUFFER POWER IN A SYSTEM WITH A SINGLE MEMORY CLOCK PER MEMORY MODULE

Simplified Explanation

The clock buffer device for a memory module described in the abstract includes two phase-locked loops (PLLs) that can be selectively coupled to clock output buffers based on the configuration of the information handling system. When the first information handling system provides a clock signal on the first clock input but not the second, the device disables the second PLL and couples the output of the first PLL to the clock output buffers.

• The clock buffer device includes two PLLs, with the ability to selectively couple them to clock output buffers.
• The device can detect the configuration of the information handling system and adjust the PLL coupling accordingly.

Potential Applications

The technology described in the patent application could be applied in various electronic devices that require precise clock signals, such as computer systems, networking equipment, and communication devices.

Problems Solved

This technology solves the problem of efficiently managing clock signals in a memory module by dynamically adjusting the coupling of PLLs based on the configuration of the information handling system.

Benefits

The benefits of this technology include improved clock signal management, reduced power consumption by disabling unnecessary PLLs, and enhanced overall performance of the memory module.

Potential Commercial Applications

The technology could be commercially applied in the manufacturing of memory modules for computers, servers, and other electronic devices that require reliable clock signal distribution.

Possible Prior Art

One possible prior art for this technology could be the use of clock buffer devices with fixed PLL configurations, which may not be as flexible or efficient as the dynamically adjustable system described in the patent application.

Unanswered Questions

How does the device detect the configuration of the information handling system?

The abstract does not provide details on the specific mechanism used to detect whether the first information handling system is configured to provide a clock signal on the first input but not the second.

What is the process for disabling the second PLL?

The abstract mentions that the device disables the second PLL in response to the configuration of the information handling system, but it does not elaborate on the specific steps or mechanisms involved in this process.

Original Abstract Submitted

A clock buffer device for a memory module includes a first clock input coupled to an input of a first phase-locked loop (PLL), and a second clock input coupled to an input of a second PLL. An output of the first PLL is selectably coupled to clock output buffers, and an output of the second PLL is selectably coupled to a subset of the clock output buffers. The clock buffer device receives a first indication that a first information handling system is configured to provide a first clock signal on the first clock input but to not provide a second clock signal on the second clock input, and, in response to the indication, couples the output of the first PLL to the clock output buffers and to disables the second PLL.